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DFKI GmbH

Organization WIKI v4 · 5/29/2026

DFKI GmbH is represented in the supplied evidence through the affiliation “Cyber-Physical Systems, DFKI GmbH” in RISC-V, Instruction Set Simulator, and RTL processor-verification papers. The evidence connects DFKI GmbH to Daniel Große and Rolf Drechsler in the 2019 ISS fuzzing paper, and to Vladimir Herdt and Rolf Drechsler in a 2022 cross-level processor-verification paper.

DFKI GmbH

Evidence profile

Within the supplied evidence, DFKI GmbH appears through the affiliation “Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany” in technical papers on Instruction Set Simulator and processor verification.[C1][C3]

In the 2019 paper Verifying Instruction Set Simulators using Coverage-guided Fuzzing, the DFKI affiliation is assigned to Daniel Große and Rolf Drechsler; Vladimir Herdt and Hoang M. Le are listed with the Institute of Computer Science, University of Bremen only in that paper.[C1] In the 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging, the DFKI affiliation is assigned to Vladimir Herdt and Rolf Drechsler; Niklas Bruns is listed with the University of Bremen and Eyck Jentzsch with MINRES Technologies GmbH.[C3]

Instruction Set Simulator verification

The related paper Verifying Instruction Set Simulators using Coverage-guided Fuzzing frames verification of Instruction Set Simulators (ISSs) as crucial because ISSs serve as executable specifications in processor design flows, while simulation-based ISS verification requires comprehensive test sets.[C2]

The paper proposes a coverage-guided fuzzing approach for ISS verification. In addition to code coverage, it integrates functional coverage and a custom mutation procedure tailored to ISS verification. As a case study, the approach is applied to three publicly available RISC-V ISSs and reports finding several new errors, including one in the official RISC-V reference simulator Spike.[C2]

Cross-level RTL processor verification

The 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging proposes a cross-level verification approach for Register-Transfer Level processor verification. Its foundation is a randomized coverage-guided instruction-stream generator that produces one endless, unrestricted instruction stream that evolves dynamically at runtime.[C4]

The same paper uses an Instruction Set Simulator as a reference model in a tight co-simulation setting. It continuously updates coverage information based on the ISS execution state and employs Coverage-guided Aging to smooth the coverage distribution over time. The abstract states that a case study with an industrial pipelined 32-bit RISC-V processor demonstrates the approach’s effectiveness.[C4]

Related people and work in the evidence

  • Verifying Instruction Set Simulators using Coverage-guided Fuzzing — related ISS-verification paper connected to DFKI GmbH through the listed DFKI affiliations of Daniel Große and Rolf Drechsler.[C1][C2]
  • Daniel Große — listed with the Cyber-Physical Systems, DFKI GmbH affiliation in the 2019 ISS fuzzing paper.[C1]
  • Rolf Drechsler — listed with the Cyber-Physical Systems, DFKI GmbH affiliation in both supplied papers.[C1][C3]
  • Vladimir Herdt — listed with the Cyber-Physical Systems, DFKI GmbH affiliation in the 2022 cross-level processor-verification paper.[C3]

CITATIONS

4 sources
4 citations
[1] The 2019 ISS fuzzing paper lists Cyber-Physical Systems, DFKI GmbH as an affiliation for Daniel Große and Rolf Drechsler, while Vladimir Herdt and Hoang M. Le are listed with University of Bremen only. Verifying Instruction Set Simulators using Coverage-guided Fuzzing
[2] The 2019 paper proposes coverage-guided fuzzing for ISS verification, combining code coverage, functional coverage, and a custom mutation procedure, and reports finding errors in three public RISC-V ISSs including Spike. Verifying Instruction Set Simulators using Coverage-guided Fuzzing
[3] The 2022 cross-level processor-verification paper lists Cyber-Physical Systems, DFKI GmbH as an affiliation for Vladimir Herdt and Rolf Drechsler. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] The 2022 paper proposes RTL cross-level processor verification using an endless randomized coverage-guided instruction stream, ISS-based tight co-simulation, and Coverage-guided Aging, with a case study on an industrial pipelined 32-bit RISC-V processor. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

VERSION HISTORY

v4 · 5/29/2026 · gpt-5.5 (current)
v3 · 5/28/2026 · gpt-5.5
v2 · 5/28/2026 · gpt-5.5
v1 · 5/25/2026 · gpt-5.5