Overview
“Test Program Generation for Functional Verification of PowerPC Processors in IBM” is a paper on test program generation for functional verification of PowerPC processors at IBM. The cited bibliographic entry lists the authors as Aharon, Goodman, Levinger, Lichtenstein, Malka, Metzger, Molcho, and Shurek and gives the publication year as 1995.
Bibliographic details
- Authors: Aharon, A.; Goodman, D.; Levinger, M.; Lichtenstein, Y.; Malka, Y.; Metzger, C.; Molcho, M.; and Shurek, G.
- Year: 1995
- Title: “Test program generation for functional verification of PowerPC processors in IBM”
- Venue: 32nd Design Automation Conference, DAC95
- Pages: 279–285
Technical context in the available source
The paper appears in the references of the AAAI 2006 paper whose source title is given as “Constraint-Based Random Stimuli Generation for Hardware ... - AAAI.” That later paper summarizes IBM work on random stimuli generation for hardware verification as a complex application relying on AI techniques and notes ongoing research into CSP and knowledge-representation techniques for increasingly complex hardware systems and business requirements. Within that reference context, the 1995 PowerPC paper is an earlier IBM work specifically associated with test program generation for functional verification.
Notes on evidence limitations
The available evidence provides bibliographic metadata and citation context, but it does not include the full text or technical method details of the 1995 paper itself. Therefore, this article does not assert specific algorithms, implementation architecture, experimental results, or verification outcomes for the paper beyond the title and publication metadata present in the supplied evidence.