RVA23 Profile

Concept WIKI v1 · 5/26/2026

RVA23 is identified in the evidence as a new RISC-V profile supported by a RISC-V verification flow. The available evidence discusses RVA23 only in the context of verification readiness, compliance-oriented test generation, and coverage of privilege-related features such as MMU, PMP, hypervisor, and vector extensions.

RVA23 Profile

Overview

RVA23 is identified as one of the new RISC-V profiles supported by a described RISC-V verification methodology.^[1] The provided evidence does not define the architectural contents or mandatory feature set of RVA23; it only establishes that the verification flow is intended to support the RVA23 profile alongside RVA22.^[1]

Verification context

The evidence frames RVA23 support as part of a “future-ready compliance” verification flow for RISC-V designs.^[1] In that same context, the flow is described as covering critical privilege specifications, including MMU, PMP, hypervisor, and vector extensions.^[2]

The methodology combines constrained-random stimulus and directed test suites. STING is described as generating portable, self-checking bare-metal programs for RISC-V, supporting constrained-random and directed stimulus across simulation, emulation, FPGA prototypes, and silicon.^[3] ImperasTS suites are described as self-checking and as automatically comparing results against a reference model, helping uncover subtle design issues and accelerate coverage closure.^[4]

Lifecycle portability

The evidence states that tests developed during RTL bring-up can remain useful in later validation stages and silicon, enabling a “shift-left” methodology.^[5] It also states that the methodology is portable across simulation, emulation, FPGA prototyping, and silicon.^[6]

Scope note

Because the provided evidence does not specify the RVA23 profile’s architectural requirements, this article is limited to the profile’s stated verification support and associated RISC-V validation methodology.

LINKED ENTITIES

6 links

RISC-V profile_family

RVA22 Profile related_profile

STING verification_tool_context

ImperasTS verification_tool_context

PMP covered_privilege_feature

Vector Extensions covered_extension_area

CITATIONS

6 sources

6 citations

[1] RVA23 is identified as one of the new RISC-V profiles supported by the verification flow, alongside RVA22. RISC-V test generation: random, directed, and coverage

[2] The flow is described as future-ready for compliance and as covering MMU, PMP, hypervisor, and vector extensions. RISC-V test generation: random, directed, and coverage

[3] STING is described as a RISC-V bare-metal functional verification tool that generates portable, self-checking programs and supports constrained-random and directed stimulus. RISC-V test generation: random, directed, and coverage

[4] ImperasTS suites are described as self-checking and as automatically comparing results against a reference model. RISC-V test generation: random, directed, and coverage

[5] Tests developed during RTL bring-up remain useful through later validation stages and silicon, enabling shift-left verification. RISC-V test generation: random, directed, and coverage

[6] The methodology is described as portable across simulation, emulation, FPGA prototyping, and silicon. RISC-V test generation: random, directed, and coverage