RVA23 Profile
ConceptRVA23 is identified in the evidence as a new RISC-V profile supported by a RISC-V verification flow. The available evidence discusses RVA23 only in the context of verification readiness, compliance-oriented test generation, and coverage of privilege-related features such as MMU, PMP, hypervisor, and vector extensions.
First seen 5/26/2026
Last seen 5/26/2026
Evidence 1 chunks
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RVA23 Profile
Overview
RVA23 is identified as one of the new RISC-V profiles supported by a described RISC-V verification methodology.[1] The provided evidence does not define the architectural contents or mandatory feature set of RVA23; it only establishes that the verification flow is intended to support the RVA23 profile alongside RVA22.[1]
NEIGHBORHOOD
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2 connectionsRVA23 is a RISC-V profile specification that is part of the broader RISC-V ISA ecosystem.
The hybrid verification flow supports and targets new RISC-V profiles including RVA23.
LINKED ENTITIES
6 linksRISC-V profile_family The evidence explicitly describes RVA23 as one of the new RISC-V profiles.
RVA22 Profile related_profile The evidence names RVA22 and RVA23 together as new RISC-V profiles supported by the flow.
STING verification_tool_context The evidence describes STING as a RISC-V bare-metal functional verification tool in the same verification flow that supports RVA23.
ImperasTS verification_tool_context The evidence describes ImperasTS directed suites as part of the RISC-V verification methodology that supports new profiles including RVA23.
PMP covered_privilege_feature The evidence says the flow covers critical privilege specifications including PMP.
Vector Extensions covered_extension_area The evidence says the flow covers critical privilege specifications and vector extensions in the same context as new RISC-V profile support.
CITATIONS
6 sources6 citations — click to expand
[1] RVA23 is identified as one of the new RISC-V profiles supported by the verification flow, alongside RVA22. RISC-V test generation: random, directed, and coverage
[2] The flow is described as future-ready for compliance and as covering MMU, PMP, hypervisor, and vector extensions. RISC-V test generation: random, directed, and coverage
[3] STING is described as a RISC-V bare-metal functional verification tool that generates portable, self-checking programs and supports constrained-random and directed stimulus. RISC-V test generation: random, directed, and coverage
[4] ImperasTS suites are described as self-checking and as automatically comparing results against a reference model. RISC-V test generation: random, directed, and coverage
[5] Tests developed during RTL bring-up remain useful through later validation stages and silicon, enabling shift-left verification. RISC-V test generation: random, directed, and coverage
[6] The methodology is described as portable across simulation, emulation, FPGA prototyping, and silicon. RISC-V test generation: random, directed, and coverage