Handshaking Mechanism
Purpose and Motivation
In an end-to-end RTL/ISS co-simulation flow, the final stage normally parses the trace log produced by the core and the trace log produced by the chosen golden-model ISS, and compares the sets of register writebacks (correct data, to the correct registers, in the correct order) to determine correctness of a given simulation.
This register-writeback comparison model is sufficient for ordinary execution, but it breaks down when tests involve external stimulus such as interrupts and debug requests. ISS models can simulate traps caused by exceptions, but they cannot model traps caused by external stimulus. As a result, register-writeback comparison alone cannot verify that the core has:
- Entered the proper interrupt handler,
- Entered Debug Mode properly, or
- Updated CSRs correctly.
To regain verification coverage in these scenarios, the Ibex testbench makes heavy use of the handshaking mechanism provided by the RISCV-DV instruction generator, which effectively allows the core to send status information to the testbench during program execution for any analysis that is required to increase verification effectiveness.
Mechanism
The mechanism is documented in detail by Google RISCV-DV at:
https://github.com/google/riscv-dv/blob/master/docs/source/handshake.rst
The handshaking is performed by the core writing to a designated signature address, which in the Ibex testbench is fixed to:
0x8ffffffc
A small set of API tasks is provided in dv/uvm/core_ibex/tests/core_ibex_base_test.sv to enable easy and efficient integration and usage of this mechanism in the Ibex test environment.
Use Sites in the Ibex Testbench
The handshake is used in practice in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv, where it is extensively used to provide runtime verification for situations involving:
- External debug requests,
- Interrupt assertions, and
- Memory faults.
Complementary Trace-Log Comparison
To add another layer of correctness checking to the checking already provided by the handshaking mechanism, a modified version of the trace-log comparison is used. Comparing every register write performed during the entire simulation would lead to an incorrect result, because the ISS trace log will not contain any execution information in the debug ROM or in any interrupt handler code. As a result, only the final values contained in every register at the end of the test are compared against each other, since any code executed in the debug ROM and trap handlers should not corrupt register state in the rest of the program.
Flow Control
The entirety of this RTL/ISS co-simulation flow (including the handshaking mechanism and the modified register-comparison check) is controlled by the Makefile found at dv/uvm/core_ibex/Makefile.