Coverage

Concept

Coverage in hardware verification measures the extent to which generated stimuli exercise a design's behavior. It is a central quality metric in simulation-based functional processor verification, in RTL fuzzing (where tools such as Instiller aim to expand coverage), and as a component within UVM testbenches (such as the Advanced Verification Suite for RISC-V cores) where it works alongside the Memory Agent, RVFI Agent, Scoreboard, and Virtual Sequencers to ensure comprehensive verification.

First seen 5/24/2026

Last seen 6/8/2026

Evidence 5 chunks

Wiki v3

WIKI

Coverage

Coverage in hardware verification refers to the extent to which generated stimuli exercise a design's behavior. It is a central quality measure in simulation-based functional verification, in RTL (register-transfer level) fuzzing, and as a structural component of a UVM (Universal Verification Methodology) testbench, where it complements other agents and scoreboards to support comprehensive verification.^[1]^[2]^[3]

Role in Functional Verification

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

RTL Fuzzing ← uses 2e

RTL fuzzing uses coverage as a key metric for evaluating fuzzing effectiveness.

INSTILLER ← evaluates 1e

Instiller is evaluated by measuring coverage improvement over DiFuzzRTL.

INSTILLER ← uses 1e

Instiller uses coverage as a primary metric to evaluate its fuzzing effectiveness.

UVM testbench part of → 1e

The UVM Testbench contains Coverage as a sub-component.

LINKED ENTITIES

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UVM testbench PART_OF Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] Coverage in hardware verification measures the extent to which generated stimuli exercise a design's behavior. Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification

[2] Generated test programs must be valid (conform to the design specification) and of high quality (expand the design's coverage and increase the probability of bug discovery). Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification

[3] IBM's model-based test-program generation partitions the generator into a generic architecture-independent engine and a target-architecture model. Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification

[4] In the Advanced Verification Suite for RISC-V cores (EAVS-DV), Coverage is a UVM testbench component that works together with the Memory Agent, RVFI Agent, Scoreboard, and Virtual Sequencers to ensure comprehensive verification. Advanced Verification Suite for RISC-V Cores

[5] The Memory Agent drives instructions and data to the DUT and observes the program counter and data addresses; the RVFI Agent is a passive agent that monitors the connected RVFI in pipeline stages; Virtual Sequencers coordinate sequencers across agents. Advanced Verification Suite for RISC-V Cores

[6] Instiller uses an ant-colony-optimization-based input instruction distillation that produces inputs 79.3% shorter than DiFuzzRTL while maintaining original coverage, simulates realistic interruption and exception handling, and applies hardware-based seed selection and mutation. Instiller: Towards Efficient and Realistic RTL Fuzzing

[7] Instiller increases coverage by 29.4% over prior fuzzing approaches, finds 17.0% more mismatches in the targets, and achieves a 6.7% average increase in execution speed. Instiller: Towards Efficient and Realistic RTL Fuzzing

[8] Coverage-guided tracing (CGT) accelerates binary-only fuzzing by limiting coverage-tracing overhead to cases where new coverage is guaranteed; fine-grain metrics (edge coverage, hit counts) are typically required by state-of-the-art fuzzers. Same Coverage, Less Bloat: Accelerating Binary-only Fuzzing with Coverage-preserving Coverage-guided Tracing