2026-05-30
3 items 79 entities 76 connections
Processed 49 entities and 48 relations.
Register-Transfer Level (RTL) Randomized Instruction Stream Generation Coverage-guided Aging Cross-Level Processor Verification Instruction Set Simulator (ISS) Co-simulation Functional Coverage Endless Instruction Stream RISC-V Instruction Set Architecture Google RISC-V Design Verification (DV) Framework Constraint-based Test Generation Coverage-guided Fuzzing Instruction Injection Pipelined Processor Branch Prediction Control and Status Registers (CSRs) Simulation-based Verification Formal Verification Model-based Test Generation Bayesian Network Coverage-directed Test Generation Symbolic Execution Instruction Group Cross-product Coverage Points riscv-vp Verilator SystemC Coverage-Observer Instruction Generator (InstrGen) Core Adapter Comparator (RTL vs ISS) MINRES The Good Core (TGC) Genesys-Pro MicroTESK RISC-V Formal Verification Framework OneSpin 360 DV RISC-V Verification App Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging Niklas Bruns Vladimir Herdt Eyck Jentzsch Rolf Drechsler University of Bremen DFKI GmbH MINRES Technologies GmbH Google UC Berkeley Machine Learning for Test Generation RV32I Base Integer ISA Cryptographic Seed for Deterministic Randomness Google RISC-V Design Verification (DV) Framework Instruction Injection
Processed 20 entities and 19 relations.
TurboFuzz hardware fuzzing processor verification agile verification FPGA-accelerated verification Test Generation-Simulation-Coverage Feedback loop coverage convergence test case generation seed control flow inter-seed scheduling hybrid fuzzer integration feedback-driven generation simulation-based verification instruction set architecture RISC-V FPGA ASIC TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification Yang Zhong Haoran Wu
Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
source →Processed 10 entities and 9 relations.
Randal E. Bryant Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic Equality with Uninterpreted Functions (EUF) Propositional Logic Ordered Binary Decision Diagrams (BDDs) Boolean Satisfiability Checking Burch-Dill Verification Method Pipelined Processor Verification Maximally Diverse Interpretations Control Logic Abstraction