2026-05-29
4 items 168 entities 218 connections
Processed 35 entities and 42 relations.
Verifying Instruction Set Simulators using Coverage-guided Fuzzing Vladimir Herdt Daniel Große Hoang M. Le Rolf Drechsler University of Bremen DFKI GmbH Instruction Set Simulator Coverage-guided Fuzzing RISC-V libFuzzer AFL Spike Forvis RISC-V Virtual Prototype Functional Coverage Code Coverage Mutation-based Fuzzing Model-based Test Generation Constrained Random Verification Instruction Set Architecture RISC-V Torture Test Generator RISC-V ISA Tests ELF Binary Differential Testing Branch Coverage Dynamic Program Analysis CSP/SMT Solver Machine Learning for Fuzzing Control and Status Registers LLVMFuzzerTestOneInput Instruction Decoder Bayesian Network Test Generation Processor Stimulus Generation Coverage-guided Fuzzing
Processed 60 entities and 85 relations.
ProcessorFuzz CSR-transition coverage DIFUZZRTL Coverage-based Greybox Fuzzing register coverage differential testing hardware fuzzing software fuzzing Control and Status Registers Register-Transfer Level ISA simulation Finite State Machine multiplexer toggle coverage seed corpus mutation engine Transition Unit Transition Map extended ISA trace log random instruction generation coverage-directed test generation assembly program test input Time-to-Exposure Spike ISA simulator Verilator Dromajo RFUZZ TheHuzz RISC-V ISA Rocket Core BOOM Core BlackParrot Core Rocket Chip SoC Generator Chisel HDL SystemVerilog HDL mstatus CSR fflags CSR mcause CSR medeleg CSR privilege mode Physical Memory Protection MulDiv module remainder register Branch Target Buffer formal verification symbolic execution model checking ProcessorFuzz paper Sadullah Canakci Chathura Rajapaksha Leila Delshadtehrani Anoop Nataraja Michael Bedford Taylor Manuel Egele Ajay Joshi Boston University University of Washington Architectural Unit instret CSR RTL simulation Hardware Description Language
Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
source →Processed 22 entities and 26 relations.
QEMU OpenVADL Vienna Architecture Description Language (VADL) Instruction Set Simulator Dynamic Binary Translation (DBT) Tiny Code Generator (TCG) VADL Intermediate Architecture Model (VIAM) TCG Transformation Decoder Generation Instruction Set Architecture (ISA) RISC-V Cycle-Approximate Simulator C-Code Generation Lowered VIAM trans_addi TCG Translation Function Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL Johannes Zottele Matthias Raschhofer Benedikt Huber Andreas Krall Technische Universität Wien Embench
Processed 51 entities and 65 relations.
Instruction Set Simulator Instruction Set Architecture Formal Verification Complete Property Suite Interval Property Checking Bounded Model Checking Interpretive Simulation Compiled Simulation Just-in-Time Compiled Simulation Architectural State Register Transfer Level Architectural Style Properties Completeness Analysis Mapping Function Safety Property Finite State Machine Boolean Satisfiability Pre-Silicon Software Development Pipelined Processor Instruction Decoding Instruction Caching Next State Function Operation Property Design Under Verification Gate-Level Simulation Architecture Description Language ITL LISA OneSpin IPC Verification Tool Generated C++ ISS write_reg macro next_state macro decode macro instrADD property isa property Generating an Efficient Instruction Set Simulator from a Complete Property Suite Ulrich Kühne Sven Beyer Christian Pichler University of Bremen OneSpin Solutions GmbH VHDL Verilog Processor Pipeline Forwarding Logic Invariant Simulation Performance (MIPS) Freeze Variable Temporal Logic Equivalence Proof Program Counter Register File