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1,693 chars[Submitted on 14 Oct 1999 (
), last revised 6 Jul 2000 (this version, v2)]
Title:Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
View a PDF of the paper titled Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic, by Randal E. Bryant and 2 other authors
Abstract: The logic of equality with uninterpreted functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. By reducing formulas in this logic to propositional formulas, we can apply Boolean methods such as Ordered Binary Decision Diagrams (BDDs) and Boolean satisfiability checkers to perform the verification.
We can exploit characteristics of the formulas describing the verification conditions to greatly simplify the propositional formulas generated. In particular, we exploit the property that many equations appear only in positive form. We can therefore reduce the set of interpretations of the function symbols that must be considered to prove that a formula is universally valid to those that are ``maximally diverse.''
We present experimental results demonstrating the efficiency of this approach when verifying pipelined processors using the method proposed by Burch and Dill.
Submission history
From: Randal E. Bryant [
]
Thu, 14 Oct 1999 22:41:39 UTC (148 KB)
[v2]
Thu, 6 Jul 2000 21:32:34 UTC (153 KB)