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Transition Leakage

Technique WIKI v1 · 6/26/2026

Transition leakage is a physical side-channel leakage effect in CMOS circuits where the dynamic power consumption of a gate depends on both its previous and current value, allowing an idealized adversary to distinguish not only the current gate value but also whether it transitioned between zero and one.

Transition Leakage

Definition

Transition leakage is a physical leakage effect that describes the phenomenon where the dynamic power consumption of CMOS gates depends on their previous and current value [BGG+14]. It is one of several simple physical leakage effects used to model the side-channel leakage behavior of CMOS gates, alongside value leakage and glitch leakage [dGPdlP+16, MMT20, GHP+21].

Formalization

In the leakage model, the leakage of a gate g is denoted by a function λ_g whose domain and co-domain depend on the considered physical leakage effect. For simpler notation, λ_g takes both the previous state σ_{i−1} and the current state σ_i as arguments, even if it ignores σ_{i−1} in the given leakage model.

For transition leakage, the observable gate leakage is formally defined as:

λ_g(σ_{i−1}, σ_i) := g(σ_{i−1}) ‖ g(σ_i)

This represents the concatenation of the old and new gate values, thereby capturing all possible transitions.

Adversary Capability

An idealized adversary with access to transition leakage can observe not only the value of the gate in the current clock cycle, but also whether the value changed from zero to one or vice versa. Specifically, the adversary can observe both the initial value and the resulting value of each gate.

Context Within the Leakage Model

Transition leakage is studied alongside:

  • Value leakage: The earliest physical leakage effect considered in the side-channel literature [ISW03], where an idealized adversary can observe the value of any wire connected to a gate at the end of a clock cycle. Formally, λ_g(σ_{i−1}, σ_i) := g(σ_i).
  • Glitch leakage: A physical leakage effect that arises due to the change in value a gate experiences within a clock cycle [FGP+18]. A common approximation defines glitch-extended leakage as λ_g(σ_{i−1}, σ_i) := C_g(σ_i), where C_g is the computational base of the gate.

The overall leakage emitted by a circuit during the execution of a single clock cycle i corresponds to the concatenation of all the individual leakages of every single gate g ∈ G, written as ⟨λ_g(σ_{i−1}, σ_i) | g ∈ G⟩.

Application in Leakage Contracts

Transition leakage is incorporated into the formal framework of leakage contracts for processors, which specify both the functional and leakage behavior of a processor hardware circuit. Hardware compliance with a contract requires that any leakage detectable in the hardware is also leaked in the contract when computing with the same data [BGG+22]. This framework uses a relation ≼_M defined by a mapping M between hardware locations and contract locations to formalize the compliance notion.

See Also

  • Value leakage: The simplest physical leakage effect capturing only current gate values.
  • Glitch leakage: A physical leakage effect capturing intra-cycle gate transitions.
  • Leakage contracts: Formal specifications of processor hardware leakage behavior used to verify hardware compliance.

LINKED ENTITIES

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Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches USES

CITATIONS

5 sources
5 citations
[1] Transition leakage is a physical leakage effect that describes the phenomenon where the dynamic power consumption of CMOS gates depends on their previous and current value. Leakage Contracts for Processors with Transitions and Glitches
[2] An idealized adversary with access to transition leakage can observe both the initial value and the resulting value of each gate. Leakage Contracts for Processors with Transitions and Glitches
[3] The observable gate leakage for transition leakage is formally defined as λ_g(σ_{i−1}, σ_i) := g(σ_{i−1}) ‖ g(σ_i), representing the concatenation of old and new gate values. Leakage Contracts for Processors with Transitions and Glitches
[4] The leakage behavior of CMOS gates can be modeled in terms of simple physical leakage effects including value leakage, transition leakage, and glitch leakage. Leakage Contracts for Processors with Transitions and Glitches
[5] Hardware compliance with a leakage contract requires that any leakage detectable in the hardware is also leaked in the contract when computing with the same data. Leakage Contracts for Processors with Transitions and Glitches