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Random Instruction Stream

Technique WIKI v1 · 5/26/2026

A Random Instruction Stream is a processor-verification technique supported by RISCV-DV in which randomly generated instructions can be used alongside directed instructions for RISC-V verification scenarios.

Overview

A Random Instruction Stream is referenced in RISCV-DV as part of an instruction-generation flow for RISC-V processor verification. RISCV-DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification, and its feature set explicitly includes support for mixing directed instructions with a random instruction stream. [C1][C2]

Role in RISCV-DV

Within RISCV-DV, random instruction streams are one component of a broader randomized verification approach. The generator supports random forward and backward branch instructions, illegal instruction and HINT instruction generation, sub-program generation with random program calls, page-table randomization and exceptions, privileged CSR setup randomization, and randomized debug ROM support. These features can contribute to varied generated programs and verification scenarios. [C3]

Supported verification scope

The RISCV-DV generator supports the RV32IMAFDC and RV64IMAFDC instruction sets, as well as machine, supervisor, and user privileged modes. It also includes trap and interrupt handling, MMU stress-test support, instruction-generation coverage, and co-simulation with multiple instruction set simulators including Spike, riscv-ovpsim, Whisper, and sail-riscv. [C4]

Tooling requirements

Running RISCV-DV requires an RTL simulator with SystemVerilog and UVM 1.2 support. The project documentation states that the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. [C5]

LINKED ENTITIES

1 links
riscv-dv implemented_in

CITATIONS

5 sources
5 citations
[1] RISCV-DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification. chipsalliance/riscv-dv
[2] RISCV-DV supports mixing directed instructions with a random instruction stream. chipsalliance/riscv-dv
[3] RISCV-DV supports randomized or random-generation features including random forward/backward branches, illegal and HINT instruction generation, sub-program generation and random calls, page-table randomization and exceptions, privileged CSR setup randomization, and randomized debug ROM support. chipsalliance/riscv-dv
[4] RISCV-DV supports RV32IMAFDC and RV64IMAFDC, machine/supervisor/user modes, trap and interrupt handling, MMU stress tests, instruction-generation coverage, and co-simulation with Spike, riscv-ovpsim, Whisper, and sail-riscv. chipsalliance/riscv-dv
[5] Running RISCV-DV requires an RTL simulator that supports SystemVerilog and UVM 1.2, and the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. chipsalliance/riscv-dv