Overview

Lowered VIAM is an intermediate representation used in the OpenVADL QEMU-generation flow. In the presented pipeline, a VADL specification is processed into a VADL Intermediate Architecture Model (VIAM), then transformed into Lowered VIAM, and finally passed to C-Code Generation to produce a QEMU frontend. The QEMU-generation diagram shows this sequence as: VIAM → TCG Transformation → Lowered VIAM → C-Code Generation → QEMU Frontend.[pipeline]

The purpose of Lowered VIAM is to express instruction semantics in a form closer to QEMU's Tiny Code Generator (TCG). The source material summarizes the approach as automatic QEMU frontend generation by "lowering the intermediate representation (VIAM) to TCG operations."[purpose]

Role in the QEMU generation pipeline

Lowered VIAM appears after VIAM and before generated C code in the QEMU backend flow. The pipeline shown for QEMU generation includes decoder generation and a VDT path into the QEMU system, while the semantic path transforms VIAM into TCG-oriented Lowered VIAM and then emits C code for the QEMU frontend.[pipeline]

This makes Lowered VIAM the bridge between architecture-level instruction semantics and concrete TCG emission in C. It does not appear as the original architecture description; rather, it is a lowered form derived from VIAM specifically for QEMU/TCG code generation.[pipeline][purpose]

Example: RISC-V 64 ADDI

The evidence illustrates the transformation using the RISC-V 64 ADDI instruction:

X(rd) := X(rs1) + immS

In the VIAM view, the instruction is represented with field accesses, register reads, an add node, and a register write. In the Lowered VIAM view, the same instruction is represented with field nodes such as field<rs1>, field<immS>, and field<rd>, variable-like nodes for register, constant, and temporary values, and TCG-oriented operations including tcg_add and tcg_mov before instr_end.[addi-lowering]

The corresponding generated C translation function for ADDI allocates or retrieves QEMU TCG values, materializes the immediate as a TCG constant, emits tcg_gen_add_i64, and then emits tcg_gen_mov_i64 to write the result to the destination register.[generated-code]

static bool trans_addi(DisasContext *ctx, arg_addi *a) {
  TCGv_i64 reg_x_rd_dest = dest_x(ctx, a->rd);
  TCGv_i64 reg_x_rs1 = get_x(ctx, a->rs1);
  TCGv_i64 tmp_n4_0 = tcg_temp_new_i64();
  TCGv_i64 const_immS_n3 = tcg_constant_i64(a->immS);

  tcg_gen_add_i64(tmp_n4_0, reg_x_rs1, const_immS_n3);
  tcg_gen_mov_i64(reg_x_rd_dest, tmp_n4_0);

  return true;
}

Technical significance

Lowered VIAM is significant because it is the representation where OpenVADL instruction semantics have been made explicit in terms of TCG-like operations. This enables automatic generation of QEMU translation functions from VADL processor descriptions instead of hand-writing the frontend semantics directly in QEMU C code.[purpose][generated-code]

Position relative to related concepts

• VADL Intermediate Architecture Model (VIAM): Lowered VIAM is derived from VIAM by a TCG transformation step.[pipeline]
• C-Code Generation: Lowered VIAM is the direct input to the C-code generation stage that emits QEMU frontend translation code.[pipeline][generated-code]