Overview

Rajat Bahl is listed with AMD, Inc. as a contributor to the article "Generating AMD microcode stimuli using VCS constraint solver." The article credits Gregory Tang and Rajat Bahl, AMD, Inc., along with Alex Wakefield and Padmaraj Ramachandran, Synopsys Inc.

Technical context of the cited work

The article addresses verification challenges in increasingly complex microprocessor designs. It states that hand-written directed tests had become less common, with automated random test generators used instead to create microcode test sequences and cover stimulus space more efficiently.

The work describes a hierarchical constrained-random approach for generating AMD microcode stimuli. The stated goals of the approach are to accelerate generation, reduce memory consumption, improve distribution control, and bias generation toward corner cases using the Synopsys VCS constraint solver.

Method described in the article

The article describes use of SystemVerilog constraint language constructs to model microcode instruction attributes and control value distributions for individual fields. It contrasts an initial single-class prototype, where constraints for all opcodes were defined together, with a later object-oriented hierarchical design using a base class for global constraints and subclasses for groups of related opcodes.

The generator architecture described in the article has two layers:

• an upper layer implemented with a SystemVerilog random sequence construct and weighted knobs for high-level distribution control; and
• a lower layer consisting of an opcode class randomized with additional constraints and weights supplied by the upper layer.

The article reports that partitioning constraints hierarchically into smaller opcode groups drastically reduced memory requirements and increased performance compared with the larger single-class constraint problem.