Rajat Bahl
PersonRajat Bahl is listed as an AMD, Inc. contributor to the Design-Reuse article "Generating AMD microcode stimuli using VCS constraint solver," which discusses hierarchical constrained-random generation of AMD microcode stimuli using SystemVerilog constructs and the Synopsys VCS constraint solver.
First seen 5/24/2026
Last seen 6/5/2026
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Rajat Bahl is listed with AMD, Inc. as a contributor to the article "Generating AMD microcode stimuli using VCS constraint solver." The article credits Gregory Tang and Rajat Bahl, AMD, Inc., along with Alex Wakefield and Padmaraj Ramachandran, Synopsys Inc.
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8 sources8 citations — click to expand
[1] Rajat Bahl is listed with AMD, Inc. as a contributor to the article "Generating AMD microcode stimuli using VCS constraint solver." Generating AMD microcode stimuli using VCS constraint solver
[2] The article also lists Gregory Tang with AMD, Inc. and Alex Wakefield and Padmaraj Ramachandran with Synopsys Inc. Generating AMD microcode stimuli using VCS constraint solver
[3] The article discusses verification of complex microprocessor designs and the shift from hand-written directed tests toward automated random test generators for microcode test sequences. Generating AMD microcode stimuli using VCS constraint solver
[4] The article describes a hierarchical constrained-random approach intended to accelerate generation, reduce memory consumption, control distributions, and bias generation toward corner cases using the Synopsys VCS constraint solver. Generating AMD microcode stimuli using VCS constraint solver
[5] The article states that SystemVerilog constraint language constructs provide a concise way to describe microcode instructions and control field-value distributions. Generating AMD microcode stimuli using VCS constraint solver
[6] The article contrasts a single-class opcode generator with an object-oriented hierarchical design using a base class and subclasses for related opcode groups. Generating AMD microcode stimuli using VCS constraint solver
[7] The generator architecture described in the article has an upper SystemVerilog random-sequence layer with weighted knobs and a lower opcode-class layer randomized with constraints and weights. Generating AMD microcode stimuli using VCS constraint solver
[8] The article reports that hierarchical partitioning of constraints into smaller opcode groups drastically reduced memory requirements and increased performance. Generating AMD microcode stimuli using VCS constraint solver