Gregory Tang
PersonGregory Tang is identified in the provided evidence as an AMD, Inc. author of the technical article "Generating AMD microcode stimuli using VCS constraint solver." The article discusses constrained-random microcode stimulus generation using SystemVerilog and the Synopsys VCS constraint solver, including single-class and hierarchical multi-class opcode-generation approaches.
First seen 5/24/2026
Last seen 6/5/2026
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Overview
Gregory Tang is listed as an author from AMD, Inc. on the technical article "Generating AMD microcode stimuli using VCS constraint solver." The article was co-authored with Rajat Bahl of AMD, Inc. and Alex Wakefield and Padmaraj Ramachandran of Synopsys Inc. [C1]
Technical area
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5 linksAMD, Inc. affiliated_with The article byline identifies Gregory Tang and Rajat Bahl as being from AMD, Inc.
Rajat Bahl coauthor The byline lists Gregory Tang and Rajat Bahl together as authors from AMD, Inc.
Alex Wakefield coauthor The byline lists Alex Wakefield as a co-author of the same article.
Padmaraj Ramachandran coauthor The byline lists Padmaraj Ramachandran as a co-author of the same article.
Synopsys Inc. coauthor_affiliation Two co-authors of the article, Alex Wakefield and Padmaraj Ramachandran, are identified as being from Synopsys Inc.; the article also uses the Synopsys VCS constraint solver.
CITATIONS
7 sources7 citations — click to expand
[1] C1: Gregory Tang is listed as an AMD, Inc. author of the article "Generating AMD microcode stimuli using VCS constraint solver," alongside Rajat Bahl, Alex Wakefield, and Padmaraj Ramachandran. Generating AMD microcode stimuli using VCS constraint solver
[2] C2: The article discusses microprocessor verification trends, including reduced reliance on hand-written directed tests and increased use of automated random test generators for microcode test sequences. Generating AMD microcode stimuli using VCS constraint solver
[3] C3: The article explores a hierarchical constrained-random approach using the Synopsys VCS constraint solver to accelerate generation, reduce memory use, and improve distribution and biasing for corner cases. Generating AMD microcode stimuli using VCS constraint solver
[4] C4: SystemVerilog constraint-language constructs are described as a way to express microcode instruction attribute combinations and control field-value distributions. Generating AMD microcode stimuli using VCS constraint solver
[5] C5: The opcode generator architecture has an upper SystemVerilog random-sequence layer with weighted knobs and a lower randomized opcode-class layer that receives additional constraints and weights. Generating AMD microcode stimuli using VCS constraint solver
[6] C6: The article describes single-class randomization as flexible but potentially slow, and states that the opcode class contained about 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver
[7] C7: The article describes an object-oriented hierarchical approach with a global-constraint base class and related-opcode subclasses, reporting reduced memory requirements and increased performance. Generating AMD microcode stimuli using VCS constraint solver