Overview
Gregory Tang is listed as an author from AMD, Inc. on the technical article "Generating AMD microcode stimuli using VCS constraint solver." The article was co-authored with Rajat Bahl of AMD, Inc. and Alex Wakefield and Padmaraj Ramachandran of Synopsys Inc. [C1]
Technical area
The article addresses verification for increasingly complex microprocessor designs. It describes the shift away from hand-written directed tests toward automated random test generators that create microcode test sequences and improve coverage across opcode and instruction-attribute stimulus spaces. [C2]
Method described in the article
The work explores a hierarchical constrained-random method for generating AMD microcode stimuli with the Synopsys VCS constraint solver. The stated goals are to accelerate generation, reduce memory consumption, and provide distribution control and biasing for corner-case coverage. [C3]
The article explains that SystemVerilog constraint-language constructs can express microcode instructions in terms of legal attribute combinations and can control the distribution of values for individual fields. [C4]
Generator architecture
The opcode generator described in the article uses two layers. The upper layer is implemented with a SystemVerilog random sequence construct and weighted knobs for high-level distribution control. The lower layer contains the opcode class, randomized with additional constraints and weights from the upper layer. [C5]
Randomization approaches discussed
Single-class randomization
The article describes an initial or simple implementation style in which a single opcode class contains all opcode constraints. This approach is flexible because constraints can be applied between any data members, but it may slow randomization because the constraint solver must handle many random variables and a large constraint set. The described opcode class contained approximately 100 random variables and 800 constraint equations. [C6]
Hierarchical multi-class randomization
The article then describes an object-oriented hierarchical approach: a base class holds global constraints common to all opcodes, while subclasses define groups of related opcodes with similar constraints. Partitioning constraints into smaller hierarchical opcode groups is reported to drastically reduce memory requirements and increase performance. [C7]
Significance within the provided evidence
Within the available evidence, Gregory Tang's documented technical contribution is authorship of an AMD-related verification article focused on constrained-random microcode stimulus generation, SystemVerilog constraint modeling, and performance-oriented opcode-generator architecture. [C1][C3][C7]