AMD, Inc.

Organization

AMD, Inc. is represented in the provided evidence through a technical verification article co-authored by AMD personnel Gregory Tang and Rajat Bahl. The article describes hierarchical constrained-random generation of AMD microcode stimuli using SystemVerilog constructs and the Synopsys VCS constraint solver to improve stimulus distribution, reduce memory use, and increase performance in microprocessor verification.

First seen 5/24/2026

Last seen 6/4/2026

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WIKI

Technical verification work

AMD, Inc. personnel Gregory Tang and Rajat Bahl co-authored the article "Generating AMD microcode stimuli using VCS constraint solver" with Alex Wakefield and Padmaraj Ramachandran of Synopsys Inc. The article addresses verification challenges caused by increasing microprocessor design complexity and the declining practicality of hand-written directed tests.

Microcode stimulus generation

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LINKED ENTITIES

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Synopsys Inc. technical_article_coauthor The evidence names Alex Wakefield and Padmaraj Ramachandran as Synopsys Inc. authors on the same article as AMD, Inc. authors Gregory Tang and Rajat Bahl.

CITATIONS

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8 citations — click to expand

[1] AMD personnel Gregory Tang and Rajat Bahl co-authored the article with Synopsys Inc. personnel Alex Wakefield and Padmaraj Ramachandran. Generating AMD microcode stimuli using VCS constraint solver

[2] The article addresses the shift from hand-written directed tests to automated random test generators for complex microprocessor verification. Generating AMD microcode stimuli using VCS constraint solver

[3] The described random test generators create microcode test sequences and emphasize stimulus distribution across meaningful opcode and instruction-attribute values. Generating AMD microcode stimuli using VCS constraint solver

[4] The article describes using a hierarchical constrained-random approach with the Synopsys VCS constraint solver to accelerate generation, reduce memory consumption, and improve distribution and corner-case biasing. Generating AMD microcode stimuli using VCS constraint solver

[5] SystemVerilog constraint constructs are described as a concise way to express microcode instruction attribute combinations and control value distributions for individual fields. Generating AMD microcode stimuli using VCS constraint solver

[6] The generator architecture consists of an upper SystemVerilog random-sequence layer with weighted knobs and a lower opcode-class layer randomized with constraints and weights. Generating AMD microcode stimuli using VCS constraint solver

[7] The single-class opcode prototype contained approximately 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver

[8] Partitioning opcode constraints into a base class and related opcode subclasses reduced memory requirements and increased performance. Generating AMD microcode stimuli using VCS constraint solver