Technical verification work

AMD, Inc. personnel Gregory Tang and Rajat Bahl co-authored the article "Generating AMD microcode stimuli using VCS constraint solver" with Alex Wakefield and Padmaraj Ramachandran of Synopsys Inc. The article addresses verification challenges caused by increasing microprocessor design complexity and the declining practicality of hand-written directed tests.

Microcode stimulus generation

The article describes automated random test generators that create microcode test sequences. These generators aim to distribute stimuli across meaningful opcode values and other instruction attributes. The authors contrast this approach with traditional sequential randomization of instruction fields, which they report can produce verbose and redundant code while offering limited control over stimulus distributions.

Constrained-random methodology

The described method uses a hierarchical constrained-random approach with the Synopsys VCS constraint solver. The article states that SystemVerilog constraint-language constructs provide a concise way to describe microcode instruction attributes and control the distribution of values for individual fields.

An initial prototype used a single class containing constraints for all opcodes. The later object-oriented design introduced a base class containing global opcode constraints and derived subclasses for groups of related opcodes with similar constraints. According to the article, partitioning constraints hierarchically into smaller opcode groups reduced memory requirements and improved performance.

Generator architecture

The opcode generator described in the article has two layers:

• An upper layer implemented with a SystemVerilog random sequence construct and weighted knobs to control high-level item distribution.
• A lower layer consisting of an opcode class randomized with additional constraints and weights supplied by the upper layer.

The test inputs contain weighted values that guide the required instruction mix, and the constraint solver applies those weights to control the distribution of generated opcode types.

Single-class versus multi-class randomization

The article describes a single-class instruction-generation style in which all opcodes are contained in one opcode class. This design is flexible because constraints can be applied between any data members in the class, but the article notes that randomization speed may be slow because the constraint solver receives a large problem. The cited opcode class contained approximately 100 random variables and 800 constraint equations.

To reduce the randomization problem size, the opcode class was then split into multiple smaller classes, with opcodes divided into related groups. The article reports that this hierarchical partitioning reduced memory requirements and increased performance.