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Christian Pichler

Person WIKI v1 · 5/26/2026

Christian Pichler is identified in the provided evidence as a co-author of the technical paper "Generating an Efficient Instruction Set Simulator from a Complete Property Suite" and as associated with OneSpin Solutions GmbH.

Christian Pichler

Christian Pichler is listed as a co-author of the paper "Generating an Efficient Instruction Set Simulator from a Complete Property Suite", together with Ulrich Kühne and Sven Beyer. The paper header associates Pichler with OneSpin Solutions GmbH in Munich, Germany, using the email address pattern {Sven.Beyer, Christian.Pichler}@onespin-solutions.com. [C1]

Technical context

The cited paper addresses the generation of instruction set simulators (ISS) for processor development and verification. Its abstract states that ISS tools support early software development and testing before a processor is manufactured, while gate-level simulation is typically too slow for in-depth software testing and may not be available early in the design process. [C2]

The paper presents an approach for automatically generating an efficient instruction set simulator from a complete property suite used in formal processor verification. The stated goal is to obtain a simulator that corresponds to the instruction set architecture used for verification, reducing the risk that a separately implemented simulator diverges from the design or ISA. [C3]

The abstract reports that the approach was shown feasible for an industrial design and that the resulting simulator's performance was comparable to custom state-of-the-art simulators. [C4]

CITATIONS

4 sources
4 citations
[1] Christian Pichler is listed as a co-author of "Generating an Efficient Instruction Set Simulator from a Complete Property Suite" and is associated in the paper header with OneSpin Solutions GmbH. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] Instruction set simulators are described as useful for early software development and testing before processor manufacture, while gate-level simulation is described as too slow for in-depth software testing and unavailable early when only the ISA is present. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] The paper presents an approach to automatically generate an instruction set simulator from a complete property suite used for formal verification, aiming to reduce discrepancies between the ISS, design, and ISA. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] The paper reports feasibility on an industrial design and performance comparable to custom state-of-the-art simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite