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Synopsys Inc.

Organization WIKI v1 · 5/25/2026

Synopsys Inc. is identified in the provided evidence through Synopsys-affiliated authors and the Synopsys VCS constraint solver, which was used in a hierarchical constrained-random approach for generating AMD microcode verification stimuli.

Overview

Synopsys Inc. appears in the provided evidence as the affiliation of Alex Wakefield and Padmaraj Ramachandran, co-authors of the article "Generating AMD microcode stimuli using VCS constraint solver." The article also discusses use of the Synopsys VCS constraint solver in a verification methodology for generating AMD microcode stimuli.[1][2]

VCS constraint solver in verification

The cited article describes a hierarchical constrained-random approach intended to accelerate generation of microcode test sequences, reduce memory consumption, and improve distribution and biasing toward corner cases. This approach used the Synopsys VCS constraint solver.[2]

The article states that SystemVerilog constraint-language constructs were used to describe microcode instructions by their possible attribute combinations and to control value distributions for individual fields.[3]

Generator architecture described in the source

The opcode generator described in the article had two layers: an upper layer implemented with a SystemVerilog random sequence construct using weighted knobs, and a lower layer consisting of an opcode class randomized with constraints and weights from the upper layer. The constraint solver applied these weights to control the distribution of generated opcode types.[4]

Constraint partitioning approach

The article contrasts a single-class randomization prototype with a hierarchical object-oriented design. In the initial prototype, constraints for all opcodes were placed in one class. The article reports that this single-class approach included approximately 100 random variables and 800 constraint equations, which could slow randomization because of the size and complexity of the problem presented to the constraint solver.[5]

To reduce the randomization problem size, the article describes an object-oriented hierarchy with a base class for global opcode constraints and subclasses for groups of related opcodes. The source states that partitioning constraints into smaller opcode groups drastically reduced memory requirements and increased performance.[6]

Notes

The provided evidence does not include broader corporate history, headquarters, executive leadership, financial information, or product-line details for Synopsys Inc. beyond the Synopsys VCS constraint solver reference and Synopsys-affiliated authorship.

LINKED ENTITIES

1 links
AMD, Inc. co_authored_source_with

CITATIONS

6 sources
6 citations
[1] Synopsys Inc. is the affiliation of Alex Wakefield and Padmaraj Ramachandran in the cited article. Generating AMD microcode stimuli using VCS constraint solver
[2] The article discusses using the Synopsys VCS constraint solver in a hierarchical constrained-random approach to accelerate microcode stimulus generation, reduce memory consumption, and bias distributions toward corner cases. Generating AMD microcode stimuli using VCS constraint solver
[3] SystemVerilog constraint-language constructs were used to describe microcode instruction attribute combinations and control value distributions for individual fields. Generating AMD microcode stimuli using VCS constraint solver
[4] The described opcode generator had an upper SystemVerilog random-sequence layer with weighted knobs and a lower opcode-class layer randomized with constraints and weights. Generating AMD microcode stimuli using VCS constraint solver
[5] The single-class prototype contained constraints for all opcodes and is described as having approximately 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver
[6] The hierarchical object-oriented approach used a base class for global constraints and subclasses for related opcode groups, and the source states that this reduced memory requirements and increased performance. Generating AMD microcode stimuli using VCS constraint solver