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STIMSMITH

page table generation

Concept WIKI v1 · 5/26/2026

In the provided evidence, page table generation is described as one of the assembly-program sections produced by the CHIPS Alliance riscv-dv random instruction generator. The evidence places it within the SystemVerilog UVM-based riscv_asm_program_gen class, which generates complete RISC-V assembly programs for RISC-V IP verification.

Overview

Page table generation is identified in the evidence as one section of a generated RISC-V assembly program. The generation occurs as part of the CHIPS Alliance open-source riscv-dv random instruction generator, which is used for RISC-V processor IP verification.

The evidence states that the generated random test can be run directly with the design IP, and that different sections of the assembly program are produced by functions in the riscv_asm_program_gen class. The listed sections include initialization routines, instruction sections, data sections, stack sections, page table, interrupt handling, and exception handling.

Role in generated assembly programs

Within the evidence, page table generation is not described as a standalone tool or separate flow. Instead, it is presented as part of complete assembly-program generation performed by riscv_asm_program_gen.sv.

The same class is described as responsible for generating the complete RISC-V assembly program used to verify RISC-V IP. Therefore, page table generation should be understood as one generated program component among several sections emitted by that class.

Generation context

The assembly-generation flow begins from configuration randomization. The evidence states that riscv_instr_gen_config is randomized from riscv_instr_base_test.sv, and that this randomization determines items such as the RISC-V extension, supported privilege mode, instruction counts for main and subprograms, and whether specific instruction classes such as ebreak, dret, fence, or wfi are generated.

The main entry point described in the evidence is gen_program(). This function is characterized as the main function that generates all sections of the program and calls other functions in riscv_asm_program_gen sequentially.

Relationship to other generated sections

The evidence explicitly lists the page table alongside other assembly-program sections:

  • initialization routine
  • instruction section
  • data section
  • stack section
  • page table
  • interrupt handling
  • exception handling

This indicates that page table generation is part of a broader generated test program structure rather than an isolated artifact in the provided description.

Evidence limitations

The provided evidence confirms that page table generation exists as a section generated by riscv_asm_program_gen, but it does not provide implementation details for page table layout, page-table entry formats, address translation modes, privilege-level interactions, or the exact function names responsible specifically for page table construction.

LINKED ENTITIES

1 links
riscv-dv part_of

CITATIONS

5 sources
5 citations
[1] CHIPS Alliance developed the open-source riscv-dv random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] The riscv_asm_program_gen.sv class generates the complete RISC-V assembly program used to verify RISC-V IP. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] Assembly-program sections generated by functions in riscv_asm_program_gen include initialization routine, instruction section, data section, stack section, page table, interrupt handling, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] riscv_instr_gen_config randomization determines generation settings such as RISC-V extension, supported privilege mode, instruction counts, and whether selected instructions are generated. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] gen_program() is described as the main function that generates all sections of the program and calls other riscv_asm_program_gen functions sequentially. RISC-V source class riscv_asm_program_gen, the brain behind ...