page table generation

Concept

In the provided evidence, page table generation is described as one of the assembly-program sections produced by the CHIPS Alliance riscv-dv random instruction generator. The evidence places it within the SystemVerilog UVM-based riscv_asm_program_gen class, which generates complete RISC-V assembly programs for RISC-V IP verification.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Page table generation is identified in the evidence as one section of a generated RISC-V assembly program. The generation occurs as part of the CHIPS Alliance open-source riscv-dv random instruction generator, which is used for RISC-V processor IP verification.

The evidence states that the generated random test can be run directly with the design IP, and that different sections of the assembly program are produced by functions in the riscv_asm_program_gen class. The listed sections include initialization routines, instruction sections, data sections, stack sections, page table, interrupt handling, and exception handling.

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LINKED ENTITIES

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riscv-dv part_of The evidence identifies riscv-dv as the CHIPS Alliance open-source random instruction generator whose class structure includes riscv_asm_program_gen.

CITATIONS

5 sources

5 citations — click to expand

[1] CHIPS Alliance developed the open-source riscv-dv random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] The riscv_asm_program_gen.sv class generates the complete RISC-V assembly program used to verify RISC-V IP. RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] Assembly-program sections generated by functions in riscv_asm_program_gen include initialization routine, instruction section, data section, stack section, page table, interrupt handling, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] riscv_instr_gen_config randomization determines generation settings such as RISC-V extension, supported privilege mode, instruction counts, and whether selected instructions are generated. RISC-V source class riscv_asm_program_gen, the brain behind ...

[5] gen_program() is described as the main function that generates all sections of the program and calls other riscv_asm_program_gen functions sequentially. RISC-V source class riscv_asm_program_gen, the brain behind ...