Overview
Intel64 is identified in the evidence as the Intel64 instruction set, known informally as x86-64. The available material discusses Intel64 primarily as the architectural model that inspired Y86-64, a simpler processor ISA used for teaching and verification work.
In the cited report, Y86-64 is described as adapting many features of Intel64/x86-64 while being far simpler. It is explicitly not intended to be a full processor implementation; instead, it provides a starting point for a working model of how microprocessors are designed and implemented.
ISA role
The evidence describes an instruction set architecture model as a specification of intended processor behavior. In that model, each instruction defines effects on architectural state, including registers, the program counter, and memory. Such an ISA specification is based on a sequential model in which instructions execute in strict sequential order.
Directly evidenced x86-64 properties
| Property | Evidence-supported description |
|---|---|
| Informal name | Intel64 is known informally as x86-64. |
| Program registers | The x86-64 ISA has 16 program registers. |
| Data movement | x86-64 includes a movq data-movement instruction; in Y86-64 this is split into rrmovq, irmovq, rmmovq, and mrmovq. |
| Stack push behavior | As with x86-64, pushing first decrements the stack pointer by eight and then writes a word to the address given by the stack pointer. |
| Stack pop behavior | In the same stack-operation context, popping reads the top word on the stack and then increments the stack pointer by eight. |
Relationship to Y86-64
Y86-64 is a simplified ISA styled after Intel64. The evidence uses this relationship to contrast the two architectures: x86-64 has 16 program registers, while Y86-64 supports 15 by eliminating %r15. This reduction allows a four-bit field in Y86-64 to encode either a register or a special no-register value called RNONE.
Y86-64 also preserves or models several instruction-set ideas relevant to the Intel64-derived design context, including variable-length instruction encodings, condition codes for conditional branches and conditional moves, stack-based call/return behavior, and base-plus-displacement memory addressing. These are stated as Y86-64 properties in the evidence, not as a complete specification of Intel64.
Verification context
The provided source is a 2018 Carnegie Mellon technical report on formal verification of pipelined Y86-64 microprocessors with UCLID5. It reports that Y86-64 is a CISC-style processor design styled after the Intel64 instruction set, and that several Y86-64 pipelined variants were verified against a sequential reference model. The report states that the verified pipeline processors generate the same results as the sequential reference model for all possible programs.