Intel64 (x86-64) ISA

Concept

Intel64 is an instruction set known informally as x86-64. The provided evidence discusses it mainly through Y86-64, a much simpler instructional ISA that adapts many Intel64 features. Directly supported properties include that the x86-64 ISA has 16 program registers, includes a `movq` data-movement instruction, and uses stack push/pop behavior based on eight-byte stack-pointer adjustments.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Intel64 is identified in the evidence as the Intel64 instruction set, known informally as x86-64. The available material discusses Intel64 primarily as the architectural model that inspired Y86-64, a simpler processor ISA used for teaching and verification work.

In the cited report, Y86-64 is described as adapting many features of Intel64/x86-64 while being far simpler. It is explicitly not intended to be a full processor implementation; instead, it provides a starting point for a working model of how microprocessors are designed and implemented.

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NEIGHBORHOOD

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RELATIONSHIPS

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Y86-64 ← derived from 100% 2e

Y86-64 is modeled after the Intel64 (x86-64) instruction set but is much simpler.

LINKED ENTITIES

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UCLID5 used_to_verify_y86_64_processors_styled_after_intel64 The report describes using the UCLID5 verifier to verify Y86-64 pipelined microprocessor variants, and identifies Y86-64 as styled after the Intel64 instruction set.

CITATIONS

8 sources

8 citations — click to expand

[1] Intel64 is known informally as x86-64. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] Y86-64 adapts many features of Intel64/x86-64 but is far simpler and intended as a working model for processor design and implementation. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] An ISA model specifies the effect of each instruction on architectural state including registers, the program counter, and memory, using a sequential model of processing. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] The x86-64 ISA has 16 program registers, while Y86-64 supports 15 by eliminating %r15 and using a four-bit field that can also encode RNONE. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] x86-64 includes a movq data-movement instruction, which Y86-64 splits into register-register, immediate-register, register-memory, and memory-register cases. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] As with x86-64, stack pushing decrements the stack pointer by eight before writing a word, and popping reads the top word before incrementing the stack pointer by eight. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] Y86-64 has variable-length instruction encodings, condition-code-controlled branching and conditional moves, stack-based procedure calls, register-only arithmetic/logical operations, base-plus-displacement addressing, and simple consistent instruction fields. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[8] The cited report used UCLID5 to verify Y86-64 pipelined microprocessor variants and showed they generate the same results as the sequential reference model for all possible programs. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5