Overview

“Genesys-pro: innovations in test program generation for functional processor verification” is a paper on test program generation for functional processor verification. In the available evidence, it appears as reference [1] in the 2020 paper Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study.[C1]

Bibliographic information available from evidence

The cited reference lists the title as “Genesys-pro: innovations in test program generation for functional processor verification”, with publication venue abbreviated as D&T, pages 84–93, and year 2004.[C1] The visible author list in the evidence includes E. Marcus, M. Rimon, M. Vinov, and A. Ziv, preceded by a partially truncated author name ending in “ournier”.[C1]

Technical context

The 2020 RISC-V processor-verification paper discusses prior work on instruction stream generation for processor verification. It characterizes model-based approaches as approaches that separate the test generator from the architecture description, and states that prominent examples using constraint solving techniques include references [1] and [2]. Reference [1] is the Genesys-pro paper.[C2]

Because the available evidence only cites Genesys-pro through another paper’s related-work discussion and bibliography, no further details about Genesys-pro’s internal algorithms, experimental results, target processors, or tool architecture can be stated here without additional sources.

Relationship to later work

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study cites Genesys-pro as part of the prior literature on instruction stream generation for processor verification.[C2]