Overview

“Generating Instruction Streams Using Abstract CSP” is a paper by Y. Katz, M. Rimon, and A. Ziv, published in DATE in 2012, on pages 15–20. It is cited in later work on processor-verification test generation as a contribution to instruction-stream generation.

Technical positioning

A later RISC-V processor-verification case study places the paper within the broader history of model-based instruction-stream generation for processor verification. That context describes model-based approaches as separating the test generator from the architecture description, and identifies constraint-solving-based methods as prominent in this area.

Within that discussion, “Generating Instruction Streams Using Abstract CSP” is characterized as an optimized test-generation framework. The cited technical property of the framework is that it propagates constraints among multiple instructions in an effective manner.

Relationship to later RISC-V verification work

The paper is referenced as prior work by “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study”, which proposes a RISC-V-focused cross-level RTL verification approach using an endless instruction stream evolved during simulation and an Instruction Set Simulator as a reference model in tightly coupled co-simulation. In that later paper’s comparison, prior instruction-stream generation approaches are contrasted with the authors’ RISC-V-targeted RTL verification method.