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Checkpoint Table

Concept WIKI v1 · 5/28/2026

A Checkpoint Table (CKPT) is a hardware array in a register-renaming stage that stores snapshots of the Register Alias Table when branch instructions are encountered, enabling faster restoration after pipeline flushes caused by branch mispredictions.

Overview

A Checkpoint Table (CKPT) is a hardware array used in a processor register-renaming stage. In the cited RISC-V superscalar processor design, the register-renaming stage includes a Free List (FL), a Register Alias Table (RAT), and the Checkpoint Table.[C1]

Role in register renaming

The CKPT stores snapshots of the RAT. A snapshot is taken whenever an incoming branch instruction is encountered.[C2] Since the RAT holds the most recent mapping from logical register specifiers to physical destination registers, saving RAT snapshots gives the processor a way to recover earlier rename state when speculative execution must be undone.[C3]

Recovery after pipeline flushes

During processor operation, the CKPT buffer helps expedite restoration of the register-renaming state after pipeline flushes. When a mispredicted branch causes a flush, the RAT is restored from the checkpoint that was saved when the offending branch instruction was originally encountered.[C4]

The recovery process also returns to the Free List all physical destination registers allocated after the offending instruction, so those physical registers can be reused.[C5]

Context

The CKPT is described as part of a register-renaming implementation that uses a merged physical register file and a pool of physical registers. In this context, logical register specifiers are replaced with physical register specifiers during renaming, and the CKPT supports speculative execution by preserving recoverable RAT states at branch boundaries.[C6]

LINKED ENTITIES

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CITATIONS

6 sources
6 citations
[1] In the cited processor design, the register-renaming stage includes a Free List, Register Alias Table, and Checkpoint Table. [PDF] UVM-based verification of RISC-V superscalar processors
[2] The Checkpoint Table is used to take snapshots of the Register Alias Table, with one snapshot taken whenever an incoming branch instruction is encountered. [PDF] UVM-based verification of RISC-V superscalar processors
[3] The Register Alias Table contains the most recent mapping of each logical register specifier to a physical destination register. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The Checkpoint Table expedites restoration of register-renaming state after pipeline flushes, and on a mispredicted branch the RAT is restored using the checkpoint saved for the offending branch instruction. [PDF] UVM-based verification of RISC-V superscalar processors
[5] During restoration after an offending instruction, physical destination registers allocated after that instruction are returned to the Free List. [PDF] UVM-based verification of RISC-V superscalar processors
[6] The described register-renaming implementation uses a pool of physical registers and replaces logical register specifiers with physical register specifiers. [PDF] UVM-based verification of RISC-V superscalar processors