Overview

MINRES Technologies GmbH is connected in the available evidence to MINRES-branded RISC-V RTL processor cores used as industrial devices under test in cross-level processor-verification research. The strongest evidence concerns a 32-bit pipelined RISC-V core of the MINRES The Good Core (TGC) series, which was used as the DUT in a Coverage-guided Aging evaluation and was described as already extensively verified with simulation-based approaches and formal techniques. [C1]

A separate cross-level testing paper reports that its approach found several serious bugs in a pipelined industrial RISC-V TGF series core and processed more than 200 million instructions per hour. [C2]

TGC RISC-V verification case study

In the DATE 2022 cross-level processor-verification case study, the DUT was the 32-bit pipelined RISC-V core of the MINRES The Good Core (TGC) series. The reference model was the ISS of an open-source SystemC-based RISC-V virtual prototype. To enable co-simulation, the industrial RTL core was translated to C++ with Verilator and integrated into a SystemC test bench with the ISS. [C1]

For the evaluation, both the RTL core and the ISS were configured for the RISC-V subset RV32IMCZicsrZifencei. The experiments were run on Ubuntu 20.04 LTS using an AMD Ryzen 7 PRO 4750U CPU at 4.1 GHz with 36 GB RAM and a SystemC simulation time limit of 1 second, corresponding to approximately 20 million instructions. [C3]

Verification architecture

The DATE 2022 approach addresses cross-level processor verification where the RTL core and ISS can have different timing and fetch behavior. Because RTL microarchitectural details such as pipelining, prefetching, and fetch buffering have to be considered, the setup uses a core adapter that checks for addresses not fetched by the ISS, fills them with randomized values not generated by the instruction generator, and forwards them to the RTL core. [C4]

The same evidence describes three verification components around the co-simulation:

• a Coverage-Observer, which measures functional coverage from the ISS execution state, applies coverage aging, and provides hints when functionality should be covered again; [C5]
• an Instruction-Injector, which evaluates those hints and injects instructions while accounting for different fetch behaviors and execution timings; [C5]
• a Comparator, which detects functional differences by comparing ISS and RTL register-value changes, logging value changes and comparing corresponding changes despite timing differences. [C6]

Reported results in the TGF-series testing paper

The FDL 2020 evidence reports that an efficient cross-level testing approach was effective in finding several serious bugs in a pipelined industrial RISC-V TGF series core. The same passage reports throughput of more than 200 million processed instructions per hour. [C2]

The paper also identifies planned future work around parallelized sessions with different random seeds, use of FPGAs to boost testing, testing the RTL core interrupt interface, evaluating additional RISC-V ISA extensions, and investigating coverage metrics that include RTL-specific coverage. [C7]

Technical relevance

Within the provided evidence, MINRES Technologies GmbH is technically relevant through:

• industrial RISC-V RTL cores used in cross-level verification studies; [C1][C2]
• a 32-bit pipelined RISC-V TGC-series core evaluated with ISS/RTL co-simulation; [C1]
• RV32IMCZicsrZifencei configuration in the reported TGC evaluation; [C3]
• Coverage-guided Aging and randomized instruction-stream based verification infrastructure; [C4][C5]
• reported bug-finding and high-throughput testing results for a pipelined industrial RISC-V TGF-series core. [C2]