Overview

Mentor Graphics appears in the provided evidence in the context of electronic design automation (EDA) verification methodology. The evidence describes the Universal Verification Methodology (UVM) as an Accellera standard built through cooperation between EDA vendors and customers, drawing on earlier verification methodologies and code bases.

Role in UVM-related methodology

The source states that UVM was formed from technologies that originated in several earlier methodologies, including Mentor's AVM and Mentor and Cadence's OVM. It also says that UVM incorporated technologies such as Resources, TLM, and Phasing, developed by Mentor and others.

The same evidence describes OVM as a documented methodology with a supporting building-block library for verification of semiconductor chip designs. In this context, Mentor Graphics is associated with both AVM and OVM as part of the technical lineage that contributed to UVM.

Technical context

The evidence places Mentor's contributions within a broader industry move toward standardizing verification processes for semiconductor IP. It describes SystemVerilog as the language of choice for verification tasks and notes that UVM became a widely adopted framework for standardized IP verification.