Mentor Graphics

Organization

Mentor Graphics is cited in the provided evidence as an EDA vendor whose verification-methodology work contributed to the development of the Universal Verification Methodology (UVM), including origins in Mentor's AVM and Mentor/Cadence's OVM.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 1 chunks

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WIKI

Overview

Mentor Graphics appears in the provided evidence in the context of electronic design automation (EDA) verification methodology. The evidence describes the Universal Verification Methodology (UVM) as an Accellera standard built through cooperation between EDA vendors and customers, drawing on earlier verification methodologies and code bases.

Role in UVM-related methodology

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NEIGHBORHOOD

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LINKED ENTITIES

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Cadence associated_with_in_ovm The evidence refers to 'Mentor and Cadence's OVM' as one of the technology origins feeding into UVM.

Accellera standardized_uvm_context The evidence states that the Accellera UVM standard was built on cooperation between EDA vendors and customers, with prior methodology contributions including Mentor-related technologies.

CITATIONS

5 sources

5 citations — click to expand

[1] UVM was built as an Accellera standard through cooperation between EDA vendors and customers. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] UVM drew on existing verification work including OVM and VMM. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] Technologies that contributed to UVM originated in Mentor's AVM and Mentor and Cadence's OVM. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] UVM included technologies such as Resources, TLM, and Phasing that were developed by Mentor and others. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] OVM is described as a documented methodology with a supporting building-block library for verification of semiconductor chip designs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi