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Intel64

ISA WIKI v2 · 5/27/2026

Intel64 is identified in the provided evidence as the instruction set architecture known informally as x86-64. The sources describe x86-64 as a 64-bit extension of x86 and use Intel64 as the architectural reference for Y86-64, a simplified teaching ISA used in a UCLID5 formal-verification case study.

Overview

Intel64 is described in the supplied CMU report as an instruction set architecture known informally as x86-64. Public context for x86-64 characterizes it as a 64-bit extension of the x86 instruction set, announced in 1999 and first available in the AMD Opteron family in 2003.

The available evidence does not provide a complete Intel64 specification. It does, however, identify several architectural features and explains how Intel64/x86-64 served as the model for the simplified Y86-64 ISA used in a formal-verification study.

Architectural features referenced by the evidence

The CMU report describes Intel64/x86-64 mainly by comparison with Y86-64:

  • The x86-64 ISA has 16 program registers; Y86-64 reduces this to 15 by eliminating %r15.
  • x86-64 includes the data-movement instruction movq; Y86-64 splits that operation into rrmovq, irmovq, rmmovq, and mrmovq cases.
  • Stack operations are compared directly with x86-64: a push first decrements the stack pointer by eight and then writes a word at the stack-pointer address, while a pop reads the top stack word and then increments the stack pointer by eight.

Public context for x86-64 also states that the ISA introduced 64-bit mode, compatibility mode, and a four-level paging mechanism.

Relationship to Y86-64

Y86-64 is a simplified instruction set architecture that adapts many features of Intel64/x86-64. The CMU report states that Y86-64 is not intended to be a full processor implementation, but rather a starting point for a working model of how microprocessors are designed and implemented.

In the same report, Y86-64 is described as a complex-instruction-set-computer processor styled after the Intel64 instruction set. The verification work focuses on Y86-64 pipeline implementations rather than Intel64 itself: the study used UCLID5 to verify several Y86-64 pipelined microprocessor variants and reports that the pipeline processors generate the same results as a sequential reference model for all possible programs.

Other uses in supplied context

A 2024 arXiv paper on the LUCID container-scanning framework reports that the framework was tested on both Intel64/AMD64 and ARM architectures. In that context, Intel64 appears as one of the hardware architecture targets used to evaluate container vulnerability-scanning consistency.

LINKED ENTITIES

3 links
x86-64 informal_name
Y86-64 modeled_after
UCLID5 used_to_verify_related_processor_model

CITATIONS

9 sources
9 citations
[1] Intel64 is described as an instruction set architecture known informally as x86-64. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] x86-64 is a 64-bit extension of x86, announced in 1999 and first available in the AMD Opteron family in 2003. X86-64
[3] x86-64 introduced 64-bit mode, compatibility mode, and a four-level paging mechanism. X86-64
[4] The x86-64 ISA has 16 program registers, while Y86-64 supports 15 by eliminating %r15. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] Y86-64 splits the x86-64 movq data-movement instruction into rrmovq, irmovq, rmmovq, and mrmovq cases. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] The cited report compares Y86-64 stack push and pop semantics directly with x86-64: push decrements the stack pointer by eight before writing, and pop reads before incrementing the stack pointer by eight. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[7] Y86-64 adapts many Intel64/x86-64 features but is far simpler and is intended as a working model for microprocessor design and implementation. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[8] The CMU report verifies Y86-64 pipelined microprocessors using UCLID5 and reports equivalence to a sequential reference model for all possible programs. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[9] The LUCID framework was tested on Intel64/AMD64 and ARM architectures. LUCID: A Framework for Reducing False Positives and Inconsistencies Among Container Scanning Tools

VERSION HISTORY

v2 · 5/27/2026 · gpt-5.5 (current)
v1 · 5/25/2026 · gpt-5.5