Intel64

ISA

Intel64 is identified in the provided evidence as the instruction set architecture known informally as x86-64. The sources describe x86-64 as a 64-bit extension of x86 and use Intel64 as the architectural reference for Y86-64, a simplified teaching ISA used in a UCLID5 formal-verification case study.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 2 chunks

Wiki v2

WIKI

Overview

Intel64 is described in the supplied CMU report as an instruction set architecture known informally as x86-64. Public context for x86-64 characterizes it as a 64-bit extension of the x86 instruction set, announced in 1999 and first available in the AMD Opteron family in 2003.

The available evidence does not provide a complete Intel64 specification. It does, however, identify several architectural features and explains how Intel64/x86-64 served as the model for the simplified Y86-64 ISA used in a formal-verification study.

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LINKED ENTITIES

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x86-64 informal_name The CMU report states that the Intel64 instruction set is known informally as x86-64.

Y86-64 modeled_after The CMU report says Y86-64 adapts many features of Intel64/x86-64 and is styled after the Intel64 instruction set.

UCLID5 used_to_verify_related_processor_model The CMU report uses UCLID5 to verify Y86-64 processors that are styled after Intel64.

CITATIONS

9 sources

9 citations — click to expand

[1] Intel64 is described as an instruction set architecture known informally as x86-64. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] x86-64 is a 64-bit extension of x86, announced in 1999 and first available in the AMD Opteron family in 2003. X86-64

[3] x86-64 introduced 64-bit mode, compatibility mode, and a four-level paging mechanism. X86-64

[4] The x86-64 ISA has 16 program registers, while Y86-64 supports 15 by eliminating %r15. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] Y86-64 splits the x86-64 movq data-movement instruction into rrmovq, irmovq, rmmovq, and mrmovq cases. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] The cited report compares Y86-64 stack push and pop semantics directly with x86-64: push decrements the stack pointer by eight before writing, and pop reads before incrementing the stack pointer by eight. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] Y86-64 adapts many Intel64/x86-64 features but is far simpler and is intended as a working model for microprocessor design and implementation. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[8] The CMU report verifies Y86-64 pipelined microprocessors using UCLID5 and reports equivalence to a sequential reference model for all possible programs. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[9] The LUCID framework was tested on Intel64/AMD64 and ARM architectures. LUCID: A Framework for Reducing False Positives and Inconsistencies Among Container Scanning Tools