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FLEQ.S

ISA WIKI v1 · 9/27/2026

FLEQ.S is a single-precision floating-point comparison instruction from the RISC-V Zfa extension that compares two values for less-than-or-equal-to relation, behaving like FLE.S but treating quiet NaN inputs as not signaling the invalid operation exception.

FLEQ.S

FLEQ.S is a single-precision floating-point comparison instruction defined as part of the RISC-V Zfa extension. It compares two single-precision floating-point register values, writing a boolean result that indicates whether the first operand is less than or equal to the second.

Semantics

FLEQ.S is defined analogously to the existing FLE.S instruction, with the distinguishing behavior that quiet NaN inputs do not cause the invalid operation exception flag to be set. This makes the FLEQ/FLTQ family suitable for use cases such as min/max implementations where NaN inputs are expected to propagate through comparisons silently rather than trap.

Extension membership

  • FLEQ.S belongs to the Zfa extension.
  • Zfa is a small floating-point extension derived from the base F and D extensions; it adds additional floating-point instructions including FLI, FMINM/FMAXM, FROUND/FROUNDNX, FMVH.X.D, FMVP.D.X, FLEQ/FLTQ, and FCVTMOD.W.D.
  • The full Zfa instruction set covers the .H (half-precision), .S (single-precision), and .D (double-precision) floating-point variants where applicable; FLEQ itself is defined for [HSD].

Implementation

FLEQ.S (along with the rest of the Zfa instructions) was added to the sail-riscv formal specification in commit f2d8e1b9, which introduced both the Zfa existence macro and the concrete instruction encodings for the new operations. The commit notes that FLEQ and FLTQ are defined like FLE and FLT respectively, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.

See also

  • Zfa — the parent extension to which FLEQ.S belongs.
  • FLE — the base floating-point less-than-or-equal-to instruction that FLEQ.S mirrors.
  • sail-riscv — the RISC-V Sail specification artifact in which FLEQ.S was implemented.

Citations

The summary, semantics, and historical implementation details above are drawn from the sail-riscv commit message that introduced Zfa support (commit f2d8e1b9, part of the 9b4778120 commits history).

LINKED ENTITIES

3 links
Zfa PART_OF
sail-riscv IMPLEMENTS
FLE DERIVED_FROM

CITATIONS

3 sources
3 citations
[1] FLEQ.S is a single-precision floating-point comparison instruction added as part of the RISC-V Zfa extension. Commits · 9b477812019a78510ebc7f4c7b7efbf378e64a42 · riscv/sail-riscv
[2] FLEQ is defined like FLE except that quiet NaN inputs do not cause the invalid operation exception flag to be set. Add Zfa extension support (excl. quad-precision) · riscv/sail-riscv commit f2d8e1b9
[3] FLEQ.S was implemented in sail-riscv alongside the broader Zfa support in commit f2d8e1b9, which also introduced the Zfa existence macro. Add Zfa extension support (excl. quad-precision) · riscv/sail-riscv commit f2d8e1b9