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Vienna Architecture Description Language (VADL)

Concept WIKI v1 · 5/29/2026

Vienna Architecture Description Language (VADL) is an architecture description language used in OpenVADL to specify instruction set architectures, registers, instruction formats, instruction semantics, and encodings. In the OpenVADL flow, a VADL specification is processed by a frontend into the VADL Intermediate Architecture Model (VIAM), which can then be used for synthesis of tooling such as a QEMU-based instruction set simulator frontend.

Overview

Vienna Architecture Description Language (VADL) is an architecture description language shown in OpenVADL material as a way to describe an instruction set architecture and its instructions. A VADL example for RV64I defines a register file X, an instruction format Itype, the ADDI instruction semantics, and the instruction encoding for ADDI.

instruction set architecture RV64I = {
  register X : Bits<5> -> Bits<64>
  format Itype : Bits<32> =
  { imm    : Bits<12>
  , rs1    : Bits<5>
  , rd     : Bits<5>
  , opcode : Bits<7>
  , ...
  , immS = imm as SInt<32>
  }
  instruction ADDI : Itype = X(rd) := X(rs1) + immS
  encoding ADDI = {opcode = 0b001'0011, funct3 = 0b000}
}

This example indicates that VADL can express at least:

  • an instruction set architecture declaration;
  • typed register definitions;
  • bit-level instruction formats and fields;
  • derived/immediate fields such as immS;
  • instruction semantics such as register assignment; and
  • instruction encodings.

Role in the OpenVADL flow

In the OpenVADL overview, a VADL specification is an input to a frontend. The frontend produces a VIAM Architecture, after which the flow includes synthesis and simulator-generation paths. The slides show outputs or targets including an assembler and linker, compiler, cycle-approximate simulator, QEMU simulator, and hardware.

For QEMU simulator generation, the presented flow takes VIAM, performs TCG transformation, lowers VIAM, generates C code, and produces a QEMU frontend. The generated frontend executes guest programs using QEMU’s infrastructure.

Relationship to VIAM

The VADL Intermediate Architecture Model (VIAM) is shown as an intermediate representation of architecture behavior. For the RISC-V 64 ADDI instruction, the VIAM diagram represents field accesses, register reads and writes, and an addition corresponding to the VADL semantic expression:

X(rd) := X(rs1) + immS

The slides also show a lowered VIAM form in which the operation is represented in terms of variables and TCG-like operations such as tcg_add and tcg_mov.

QEMU-generation use case

The cited OpenVADL presentation describes automatic generation of a QEMU-based instruction set simulator from a processor description in OpenVADL. Its conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations. The generated example includes C code for translating RISC-V 64 ADDI, using QEMU TCG helper calls such as tcg_gen_add_i64 and tcg_gen_mov_i64.

The same presentation reports evaluation results for generated QEMU frontends on RISC-V 64 IM and AArch64 Embench workloads, and concludes that the generated frontend achieved up to 44% lower runtime than upstream in the reported evaluation.

LINKED ENTITIES

2 links
OpenVADL USES
VADL Intermediate Architecture Model (VIAM) DERIVED_FROM

CITATIONS

6 sources
6 citations
[1] VADL can describe an instruction set architecture, registers, instruction formats, instruction semantics, and encodings, as illustrated by the RV64I ADDI example. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] In the OpenVADL overview, a VADL specification is processed by a frontend into a VIAM Architecture and is part of a flow that targets tools such as assemblers/linkers, compilers, simulators, QEMU, and hardware. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] The QEMU-generation flow uses VIAM, TCG transformation, lowered VIAM, and C-code generation to produce a QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] VIAM represents the RISC-V 64 ADDI behavior corresponding to the VADL expression X(rd) := X(rs1) + immS, including field accesses, register reads/writes, and addition. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[5] OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[6] The presentation reports that the generated QEMU frontend achieved up to 44% lower runtime than upstream in the reported evaluation. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL