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UVM (Universal Verification Methodology)

Concept WIKI v1 · 5/26/2026

UVM is identified in the evidence as Universal Verification Methodology and is used with SystemVerilog in Google’s RISC-V DV verification approach to continuously generate constrained-random RISC-V instruction streams.

Overview

UVM (Universal Verification Methodology) is referenced as part of a SystemVerilog-based verification flow in the RISC-V DV test-generation approach. In the cited processor-verification context, RISC-V DV by Google uses SystemVerilog in combination with UVM to continuously generate RISC-V instruction streams from constrained-random descriptions. Each generated instruction stream represents a test case. [C1]

Role in the cited verification flow

The evidence places UVM in a simulation-oriented verification workflow for RISC-V processors. RISC-V DV generates instruction streams and provides a high-level co-simulation interface that compares results between different simulators using execution log files. [C2]

RISC-V DV is described as supporting a large set of features, including multiple RISC-V instruction-set extensions and CSR testing capabilities. [C3]

Reported constraints of the referenced UVM-based flow

The cited source reports two major disadvantages for RISC-V DV, the framework using SystemVerilog and UVM in this context:

  • generated instruction streams are restricted to avoid infinite loops and platform-dependent memory-access operations; and
  • the framework has significant performance overhead because it is generic and aims to support a wide range of simulators and RTL cores. [C4]

These constraints are described for the RISC-V DV framework in the cited source, not as general properties of UVM itself.

Context among other RISC-V verification approaches

The source contrasts RISC-V DV with other RISC-V verification methods, including model-based test generation, coverage-guided fuzzing, formal methods, and simulation-based methods. The same passage notes that formal methods can provide correctness guarantees but are harder to apply and may have complexity or scalability issues, so they should be complemented by simulation-based methods. [C5]

LINKED ENTITIES

2 links
SystemVerilog used_with
riscv-dv used_by

CITATIONS

5 sources
5 citations
[1] C1: RISC-V DV by Google uses SystemVerilog in combination with UVM (Universal Verification Methodology) to continuously generate RISC-V instruction streams from constrained-random descriptions, and each instruction stream is a test case.
[2] C2: RISC-V DV provides a high-level co-simulation interface to compare results between different simulators via execution log files.
[3] C3: RISC-V DV supports features including several RISC-V instruction-set extensions and CSR testing capabilities.
[4] C4: The cited source reports disadvantages of RISC-V DV: restricted generated instruction streams to avoid infinite loops and platform-dependent memory accesses, and significant performance overhead due to its generic support goals.
[5] C5: The source contrasts RISC-V DV with model-based test generation, coverage-guided fuzzing, formal methods, and simulation-based methods, and says formal methods should be complemented by simulation-based methods because of difficulty, complexity, and potential scalability issues.