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UVM (Universal Verification Methodology)

Concept

UVM is identified in the evidence as Universal Verification Methodology and is used with SystemVerilog in Google’s RISC-V DV verification approach to continuously generate constrained-random RISC-V instruction streams.

First seen 5/26/2026
Last seen 5/26/2026
Evidence 1 chunks
Wiki v1

WIKI

Overview

UVM (Universal Verification Methodology) is referenced as part of a SystemVerilog-based verification flow in the RISC-V DV test-generation approach. In the cited processor-verification context, RISC-V DV by Google uses SystemVerilog in combination with UVM to continuously generate RISC-V instruction streams from constrained-random descriptions. Each generated instruction stream represents a test case. [C1]

Role in the cited verification flow

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NEIGHBORHOOD

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RELATIONSHIPS

1 connections
riscv-dv ← uses 100% 1e
RISC-V DV leverages UVM for constrained-random test generation.

LINKED ENTITIES

2 links
SystemVerilog used_with The evidence states that RISC-V DV leverages SystemVerilog in combination with UVM.
riscv-dv used_by The evidence describes RISC-V DV by Google as using SystemVerilog together with UVM for test generation.

CITATIONS

5 sources
5 citations — click to expand
[1] C1: RISC-V DV by Google uses SystemVerilog in combination with UVM (Universal Verification Methodology) to continuously generate RISC-V instruction streams from constrained-random descriptions, and each instruction stream is a test case.
[2] C2: RISC-V DV provides a high-level co-simulation interface to compare results between different simulators via execution log files.
[3] C3: RISC-V DV supports features including several RISC-V instruction-set extensions and CSR testing capabilities.
[4] C4: The cited source reports disadvantages of RISC-V DV: restricted generated instruction streams to avoid infinite loops and platform-dependent memory accesses, and significant performance overhead due to its generic support goals.
[5] C5: The source contrasts RISC-V DV with model-based test generation, coverage-guided fuzzing, formal methods, and simulation-based methods, and says formal methods should be complemented by simulation-based methods because of difficulty, complexity, and potential scalability issues.