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UVM testbench

Concept WIKI v2 · 5/28/2026

A UVM testbench is a Universal Verification Methodology-based verification environment. In the cited RISC-V vector accelerator work, it provided a reusable and extendable infrastructure with per-interface agents, virtual sequences, synchronization events, a scoreboard connected to a Spike reference model, assertions, functional coverage, and regression/CI support.

Overview

In the cited RISC-V vector accelerator verification project, the UVM testbench was the central verification environment built around the Universal Verification Methodology. The authors selected UVM because it supports modular, scalable, and reusable verification environments, and they describe the resulting infrastructure as an industrial-grade approach combining a UVM testbench, a reference model, assertions, and coverage. [C1]

The environment targeted a decoupled RISC-V vector accelerator connected to a scalar core through the Open Vector Interface (OVI). It performed step-by-step co-simulation of vector instructions using Spike as the instruction-set simulator and reference model. [C2]

Architecture

The testbench used a UVM top module that instantiated the UVM environment. Because the design interface was divided into multiple semi-independent OVI sub-interfaces, the environment created one UVM agent for each specific sub-interface. For example, the issue sub-interface had an agent containing a sequencer, driver, and monitor connected to a virtual interface. [C3]

Each virtual sequence created interface-specific transactions and sent them to the corresponding interface. When the driver received a transaction, it stimulated the relevant sub-interface with the transaction values. A monitor captured the interface state and sent it back to the virtual sequence through the sequencer, allowing the sequence to react and generate new stimulus. [C4]

Because the sub-interfaces were unique but interdependent, the environment used UVM events to keep them synchronized. The evidence notes that these events could transmit data along with the trigger, which helped virtual-sequence intercommunication. [C5]

Stimulus and execution flow

The high dependence among sub-interfaces made fully constrained-random stimulus generation difficult. The implemented strategy randomized only the instructions driven into the issue sub-interface, while the other sub-interfaces reacted according to those driven instructions. [C6]

After an instruction was fed through the issue agent, the UVM environment followed the vector processing unit instruction execution flow. This involved observing or stimulating the DISPATCH interface, where each instruction was confirmed or discarded in instruction order, and the COMPLETED interface, where the monitor observed a completion flag and created a transaction at the end of a confirmed instruction. [C7]

Scoreboard and reference model

The testbench used a UVM scoreboard to evaluate DUT results. The scoreboard compared the vector processing unit results with outputs from a reference model that predicted expected behavior from the inputs. The project used the RISC-V ISA simulator Spike for co-simulation in the UVM environment. [C8]

Spike had two roles in the environment: it acted as a scalar core that executed scalar instructions and provided vector instructions to UVM in program order, and it acted as a golden/reference model for checking DUT results. [C9]

The scoreboard was connected to the completed monitor. When an instruction finished, a comparison method was executed. For vector-register results that were not directly visible as VPU outputs, the environment accessed the destination vector register at completion time and included the destination register value extracted from Spike for comparison. [C10]

Assertions

The verification environment used SystemVerilog Assertions to improve observability and check that the OVI interface behaved as expected. More than 50 SVA properties were implemented. During early UVM testbench development, these assertions helped identify both VPU bugs and problems in UVM stimulus, with many properties targeting memory-related sub-interfaces and OVI conformance. [C11]

Functional coverage and regression use

The team defined and implemented a functional coverage plan, mainly checking items directly observable at the VPU interface, such as instructions and execution parameters. [C12]

The broader infrastructure included automated constrained-random test generation, simulation, error reporting, and CI/CD support. The authors report finding 3005 errors and reaching 95.79% functional coverage. [C13]

Maintenance lesson

The authors later observed that distributing communication across several agents complicated maintenance, extension, and performance. They suggested that a future single-agent approach could simplify sub-interface communication and future environment expansion. [C14]

LINKED ENTITIES

6 links
Functional Verification of a RISC-V Vector Accelerator INTRODUCES
Co-simulation USES
UVM scoreboard USES
UVM agent USES
virtual sequence USES
Functional Coverage USES

CITATIONS

14 sources
14 citations
[1] C1: The project used UVM because it supports modular, scalable, reusable verification environments and presented an industrial-grade verification approach with a UVM testbench, reference model, assertions, and coverage. Functional Verification of a RISC-V Vector Accelerator
[2] C2: The environment verified a decoupled RISC-V vector accelerator connected through OVI and used Spike for step-by-step co-simulation/reference modeling. Functional Verification of a RISC-V Vector Accelerator
[3] C3: The UVM top module instantiated the environment, and the environment used one agent per semi-independent sub-interface; the issue agent included a sequencer, driver, and monitor connected to a virtual interface. Functional Verification of a RISC-V Vector Accelerator
[4] C4: Virtual sequences created interface-specific transactions, drivers stimulated sub-interfaces, and monitors returned captured interface state through sequencers so sequences could react. Functional Verification of a RISC-V Vector Accelerator
[5] C5: UVM events synchronized the interdependent sub-interfaces and could transmit data with the trigger. Functional Verification of a RISC-V Vector Accelerator
[6] C6: Because constrained-random stimulus generation was complicated by sub-interface dependence, only the issue-sub-interface instructions were randomized and other sub-interfaces reacted to the driven instructions. Functional Verification of a RISC-V Vector Accelerator
[7] C7: After issue-agent stimulus, the UVM environment followed the VPU execution flow through DISPATCH confirmation/discard and COMPLETED transaction creation. Functional Verification of a RISC-V Vector Accelerator
[8] C8: The UVM scoreboard compared VPU results against a reference model, and Spike was used for co-simulation in the UVM environment. Functional Verification of a RISC-V Vector Accelerator
[9] C9: Spike acted both as a scalar core providing vector instructions to UVM in program order and as a golden/reference model. Functional Verification of a RISC-V Vector Accelerator
[10] C10: The scoreboard connected to the completed monitor, executed a comparison when an instruction finished, and included destination vector-register values from Spike for checking. Functional Verification of a RISC-V Vector Accelerator
[11] C11: The environment implemented more than 50 SystemVerilog Assertions for OVI/interface behavior, and they helped identify VPU bugs and UVM stimulation problems. Functional Verification of a RISC-V Vector Accelerator
[12] C12: The team defined a functional coverage plan focused on directly observable VPU-interface items such as instructions and execution parameters. Functional Verification of a RISC-V Vector Accelerator
[13] C13: The infrastructure included automated constrained-random test generation, simulation, error reporting, and CI/CD, found 3005 errors, and reached 95.79% functional coverage. Functional Verification of a RISC-V Vector Accelerator
[14] C14: The authors found that distributing communication across several agents complicated maintenance, extension, and performance, and proposed considering a single-agent approach in future work. Functional Verification of a RISC-V Vector Accelerator

VERSION HISTORY

v2 · 5/28/2026 · gpt-5.5 (current)
v1 · 5/27/2026 · gpt-5.5