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RVFI

Concept WIKI v2 · 5/30/2026

RVFI, the RISC-V Formal Interface, is used in the provided evidence as a per-instruction observation interface for RISC-V verification. TestRIG uses RVFI to observe architectural state changes after each instruction and compare execution traces between models, simulators, and simulated hardware implementations; RVFI-DII is used as a replay/interface context for TestRIG traces.

Overview

RVFI is identified in the evidence as the RISC-V Formal Interface standard. In TestRIG, RVFI is used to observe the change in state after each instruction of the RISC-V implementation under test. This makes RVFI a trace/reporting interface for comparing how an implementation behaves against a model or simulator at instruction granularity.

Role in TestRIG

TestRIG is a randomized testing framework for RISC-V implementations. Its workflow generates random instruction sequences, executes the same sequences on the model and the implementation under test, and compares execution traces in tandem execution. The cited paper emphasizes that this approach does not prove equivalence, but it can demonstrate divergence and is usable during development.

Within that workflow, RVFI supplies the observation side: TestRIG uses the RISC-V Formal Interface standard to observe the architectural state change after each instruction. Test injection is handled separately by Direct Instruction Injection, where the next instruction is supplied by the test harness rather than fetched normally according to the CPU program counter.

Relationship to RVFI-DII

RVFI-DII appears in the evidence as an interface/replay context connected to TestRIG traces. In the evaluation flow described for RISCV-DV, TestRIG traces are produced from the Spike simulator executing tests and then replayed through RVFI-DII while measuring Sail RISC-V model coverage.

Verification use cases

The evidence supports two main RVFI-related verification patterns:

  • Trace-equivalence testing: TestRIG compares execution traces from an executable formal model, software ISA simulator, or simulated hardware design. RVFI provides per-instruction state observations from the implementation under test.
  • Regression from counterexamples: TestRIG can convert instruction traces to and from a human-readable format and use saved traces as regression tests for previous counterexamples.

RISCV-Formal context

A public arXiv summary for CIll describes evaluation within the RISCV-Formal framework and notes that M-extension instructions were proved against the RVFI ALTOPS substitute semantics provided by RISCV-Formal. This indicates that RVFI is also relevant as a semantic interface in formal RISC-V verification workflows beyond randomized tandem testing.

LINKED ENTITIES

3 links
TestRIG USES
RVFI-DII EXTENDS
JasperGold USES

CITATIONS

6 sources
6 citations
[1] RVFI is the RISC-V Formal Interface standard and TestRIG uses it to observe the change in state after each instruction of the implementation under test. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[2] TestRIG checks equivalence pragmatically by generating random instruction sequences, executing the same sequences on a model and implementation, and comparing execution traces; this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[3] Direct Instruction Injection supplies the next instruction from the test harness regardless of the CPU program counter, separate from RVFI's observation role. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[4] In the RISCV-DV evaluation flow, TestRIG traces are produced from Spike executing tests and replayed through RVFI-DII while measuring Sail RISC-V model coverage. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[5] TestRIG supports converting instruction traces to and from a human-readable format and using trace files as regression tests for previous counterexamples. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[6] The CIll public summary reports evaluation within the RISCV-Formal framework and notes that M-extension instructions are proved against the RVFI ALTOPS substitute semantics provided by RISCV-Formal. CIll: CTI-Guided Invariant Generation via LLMs for Model Checking

VERSION HISTORY

v2 · 5/30/2026 · gpt-5.5 (current)
v1 · 5/27/2026 · gpt-5.5