random RISC-V assembly test generation

Random RISC-V assembly test generation is represented in the evidence by the use of RISCV-DV, a Google-developed tool that generates random RISC-V assembly tests. In the cited verification environment, those generated tests were used to provide vector instructions to a VPU under test. [C1]

Role in vector verification

The generated assembly tests supplied vector instructions for VPU verification. Because the available RISCV-DV implementation targeted a later RISC-V Vector Extension version than RVV 0.7.1, parts of RISCV-DV were developed and adapted to fit the target environment. [C2]

Reported generator adaptations

The reported additions and adaptations to RISCV-DV included: [C3]

• generation of vsetvli instructions through the code;
• modification of memory-operation generation to allow changes of element width and vector length;
• an option to select the initialization pattern of data pages;
• constraints on memory addresses accessed by generated tests to avoid memory exceptions, especially for vector indexed memory instructions;
• adaptation to RVV 0.7.1.

Incremental instruction enablement

During development, many instructions were initially blacklisted from generated tests so that functional tests could run at each iteration. As a significant number of errors were fixed, instructions were gradually removed from the blacklist until all implemented instructions were enabled. [C4]

Execution and checking context

In the same verification environment, Spike had two roles: executing scalar instructions while providing vector instructions to UVM in program order, and serving as a golden/reference model for checking DUT results. [C5]