random RISC-V assembly test generation
ConceptRandom RISC-V assembly test generation is evidenced through RISCV-DV, a Google-developed tool used to generate random RISC-V assembly tests. In the cited verification environment, generated tests supplied vector instructions for a VPU, with adaptations for RVV 0.7.1, vector configuration instructions, memory constraints, data-page initialization, and incremental instruction enablement.
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random RISC-V assembly test generation
Random RISC-V assembly test generation is represented in the evidence by the use of RISCV-DV, a Google-developed tool that generates random RISC-V assembly tests. In the cited verification environment, those generated tests were used to provide vector instructions to a VPU under test. [C1]
Role in vector verification
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