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random RISC-V assembly test generation

Concept

Random RISC-V assembly test generation is evidenced through RISCV-DV, a Google-developed tool used to generate random RISC-V assembly tests. In the cited verification environment, generated tests supplied vector instructions for a VPU, with adaptations for RVV 0.7.1, vector configuration instructions, memory constraints, data-page initialization, and incremental instruction enablement.

First seen 5/27/2026
Last seen 6/1/2026
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random RISC-V assembly test generation

Random RISC-V assembly test generation is represented in the evidence by the use of RISCV-DV, a Google-developed tool that generates random RISC-V assembly tests. In the cited verification environment, those generated tests were used to provide vector instructions to a VPU under test. [C1]

Role in vector verification

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riscv-dv ← implements 99% 1e
RISCV-DV is designed to generate random RISC-V assembly tests.

CITATIONS

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5 citations — click to expand
[1] RISCV-DV is a Google-developed tool that generates random RISC-V assembly tests and was used to provide vector instructions to a VPU. source
[2] RISCV-DV targeted a later RVV version than 0.7.1, so parts were developed and adapted to fit the target environment. source
[3] Reported RISCV-DV additions included vsetvli generation, memory-operation changes for element width and vector length, data-page initialization selection, constrained memory addresses, and RVV 0.7.1 adaptation. source
[4] Instructions were initially blacklisted from generated tests during development and gradually enabled as errors were fixed. source
[5] Spike executed scalar instructions, provided vector instructions to UVM in program order, and acted as a golden/reference model for checking DUT results. source