Overview
Pre-silicon software development is the early development and testing of software for a processor before the processor is manufactured. The evidence describes this as a major application area for instruction set simulators (ISS), which enable software simulation before the target system is manufactured or even before the hardware design is finished. [C1]
Role of instruction set simulators
Instruction set simulators are important in processor and system design flows because they allow software to be executed against an abstract model of the processor. In the pre-silicon setting, this supports software testing before physical silicon exists. [C1]
The evidence contrasts ISS-based simulation with gate-level simulation. Gate-level simulation can provide cycle-accurate results, but its performance is typically not sufficient for in-depth software testing. It also cannot be used in early design phases when only the instruction set architecture (ISA) exists and the processor design is not yet complete. [C2]
For this reason, more abstract simulators are based on the ISA rather than a gate-level or cycle-accurate model. Such ISA-based simulators can achieve performance of several million instructions per second. [C3]
Accuracy and synchronization risks
A central technical risk in pre-silicon software development is that the simulator may diverge from the real processor design or from the ISA. The evidence notes that when an ISS is introduced separately from the design, the ISA has to be reimplemented for the simulator, creating a risk that the ISS is not in sync with the design or ISA. [C4]
This mismatch can lead to erroneous software: software may behave correctly in the ISS but fail when executed on the chip. [C5]
Formal-property-based simulator generation
The evidence presents an approach in which an ISS is automatically generated from a complete property suite used for formal verification of the processor. This can produce a provably correct simulator with relatively small effort. [C6]
The same source explains that formal methods can provide gap-free verification, in contrast to simulation-based methods that cannot exhaustively cover all possible inputs for large designs. In this context, a complete property suite captures the behavior of the design uniquely for each possible combination of states and inputs; after formal verification, the property set forms a functionally equivalent model of the verified design. [C7]
By reusing such a complete property suite to generate an ISS, the simulator is guaranteed to comply with the ISA used for verification and, by construction, to comply with the design. [C8]
Practical implications
The evidence positions pre-silicon software development as a tradeoff between simulation fidelity, performance, and availability during early design stages. Gate-level simulation is cycle-accurate but too slow for extensive software testing and unavailable before the design exists. ISA-based ISS models are faster and available earlier, but manually reimplementing the ISA can create correctness risks. Formal-property-based ISS generation is presented as a way to reduce that risk while retaining simulator performance suitable for software development. [C2] [C3] [C6]