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STIMSMITH

Pre-Silicon Software Development

Concept

Pre-silicon software development is the development and testing of processor software before the target processor or system is manufactured, and sometimes before the design is complete. The provided evidence describes instruction set simulators as a key mechanism for this activity because they model software execution from the instruction set architecture and can run far faster than gate-level simulation.

First seen 5/26/2026
Last seen 5/29/2026
Evidence 2 chunks
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WIKI

Overview

Pre-silicon software development is the early development and testing of software for a processor before the processor is manufactured. The evidence describes this as a major application area for instruction set simulators (ISS), which enable software simulation before the target system is manufactured or even before the hardware design is finished. [C1]

Role of instruction set simulators

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The paper mentions pre-silicon software development as a major use case for ISS.
Instruction Set Simulator uses → 100% 1e
ISS is used for pre-silicon software development.

CITATIONS

8 sources
8 citations — click to expand
[1] C1: Instruction set simulators are a major application mechanism for pre-silicon software development and enable software simulation before manufacture or design completion. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] C2: Gate-level simulation can provide cycle-accurate results but is typically too slow for in-depth software testing and cannot be used in early phases when only the ISA exists. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] C3: More abstract simulators are based on the ISA and can achieve performance of several million instructions per second. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] C4: Separating the ISS from the design requires reimplementation of the ISA and creates risk that the ISS is not synchronized with the design or ISA. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[5] C5: A discrepancy between the ISS and the design can cause software to work in the ISS but fail on chip. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[6] C6: An ISS can be automatically generated from a complete property suite used for formal processor verification, yielding a provably correct simulator with relatively small effort. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[7] C7: Formal methods can provide complete verification where properties uniquely capture behavior for each possible state and input combination, forming a functionally equivalent model after verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[8] C8: Reusing a complete property suite to generate an ISS guarantees compliance with the ISA used for verification and, by construction, with the design. Generating an Efficient Instruction Set Simulator from a Complete Property Suite