Overview
In the provided RISC-V verification context, multi-hart systems are referenced as the complex end of a verification scalability range: the described methodology is said to scale "from simple embedded cores to complex multi-hart systems." The same evidence frames this scalability as part of a broader hybrid verification approach using random stimulus, directed tests, reproducible regressions, and portable test execution across implementation platforms.
Verification approach
The cited methodology combines two main styles of test generation:
- Constrained-random stimulus with STING, intended to uncover unexpected behaviours.
- Directed ImperasTS suites, intended to provide structured compliance and feature coverage and accelerate coverage convergence.
For multi-hart systems, the key supported point is not a separate multi-hart-specific flow, but that the flow is explicitly described as scalable to such systems. The same source also states that logged seeds and directed reruns support reproducibility across regression cycles, which is important when scaling verification to more complex implementations.
Debug and coverage closure
The evidence describes a debug strategy that combines architecturally self-checking tests with lock-step compare in ImperasDV. In this approach, RTL and a golden reference model run in parallel and results are compared at instruction retirement, allowing engineers to identify mismatches immediately and simplify root-cause analysis.
Coverage closure is described as being accelerated by the combination of random exploration and directed closure:
- STING is used for broad exploration and corner-case discovery.
- ImperasTS suites are applied for compliance and targeted feature coverage.
- ImperasFC/SC results can be merged into Verdi.
- Failing cases can be replayed deterministically in VCS.
Portability and shift-left use
The evidence states that tests developed during RTL bring-up remain valuable in later validation stages and in silicon. It also states that STING generates portable, self-checking programs that can run across simulation, emulation, FPGA prototypes, and silicon. This portability supports a "shift-left" methodology, with ImperasSC enabling pre-RTL coverage analysis.
For multi-hart systems, this means the same evidence-supported verification assets are positioned as reusable across stages, from early validation through later silicon use, rather than being limited to a single execution environment.
Related RISC-V features in scope
The described flow is also presented as supporting newer RISC-V profiles and privilege-related features, including:
- RVA22 and RVA23 profiles
- MMU
- PMP and ePMP
- Hypervisor features
- Vector extensions
These features are not described as exclusive to multi-hart systems in the evidence, but they are part of the broader complex RISC-V verification scope in which multi-hart systems are mentioned.
Practical guidance from the evidence
The source recommends the following sequence for teams building or verifying RISC-V designs:
- Start broad exploration with STING to uncover subtle interactions and corner cases.
- Apply targeted ImperasTS suites for compliance, MMU, PMP, and vector extensions where coverage gaps remain.
- Integrate coverage and debug by merging ImperasFC/SC results into Verdi and replaying failing cases deterministically in VCS.
- Shift verification earlier with ImperasSC and pre-RTL stimulus coverage.