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directed instruction stream

Concept WIKI v1 · 5/26/2026

A directed instruction stream is a riscv-dv assembly-generation mechanism used by `riscv_asm_program_gen.sv` to add selected instruction streams, such as `riscv_jal_instr`, into a generated RISC-V program according to configured ratios and then randomize instruction operands before conversion to assembly.

Overview

In the riscv-dv RISC-V instruction-generation flow, a directed instruction stream is an instruction stream selected and inserted into the generated assembly program according to a configured ratio. The riscv_asm_program_gen.sv flow calls get_directed_instr_stream() and uses add_directed_instr_stream() to select the ratio for instruction generation; an example log shows Adding directed instruction stream:riscv_jal_instr ratio: 30/1000. [C1]

Role in program generation

Directed instruction streams are handled as part of gen_program(), the main function described as generating all sections of the RISC-V assembly program. After header generation and GPR initialization, generate_directed_instr_stream() is called; it decides the ratio, inserts the directed instruction stream, and randomizes the instruction. [C2]

The same flow randomizes and selects source and destination registers (rs1, rs2, and rd) based on instruction type. The resulting assembly program uses general-purpose registers from x0 to x31, with post_random() in riscv_instr helping with this randomization. [C3]

Integration with the instruction stream

After directed streams and random instructions are available, riscv_instr_sequence.generate_instr_stream() uses convert2asm() to convert the instruction stream into assembly form. The riscv_asm_program_gen flow also calls main_program[hart].generate_instr_stream() to convert the instruction stream to string format. [C4]

Directed instruction streams are therefore one part of a broader assembly-program generation pipeline that also includes program headers, GPR initialization, main and subprogram generation, host-interface instructions, and trap-handling support. [C5]

Configuration context

The generation flow is controlled by randomized riscv_instr_gen_config settings from riscv_instr_base_test.sv. These settings decide items such as the RISC-V extension, supported privilege mode, instruction counts in the main program and subprogram, and whether instructions such as ebreak, dret, fence, and wfi are generated. [C6]

The flow also checks illegal-instruction and HINT-instruction ratios; if those ratios are zero, illegal or HINT instructions are not generated. [C7]

Example

The evidence gives the following example of a directed stream being added:

riscv_asm_program_gen.sv(1552) @ 0: reporter [asm_gen] Adding directed instruction stream:riscv_jal_instr ratio: 30/1000

This shows a directed stream named riscv_jal_instr being selected with a ratio of 30/1000. [C1]

CITATIONS

7 sources
7 citations
[1] Directed instruction streams are selected through `get_directed_instr_stream()` and ratio selection from `add_directed_instr_stream()`, with an example `riscv_jal_instr` ratio of `30/1000`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] `gen_program()` is the main function for generating all sections of the program, and `generate_directed_instr_stream()` decides the ratio, inserts the directed instruction stream, and randomizes the instruction. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] The directed-generation flow randomizes and selects `rs1`, `rs2`, and `rd` based on instruction type and produces instructions using GPRs `x0` through `x31`, with `post_random()` in `riscv_instr` helping. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] `riscv_instr_sequence.generate_instr_stream()` uses `convert2asm()`, and `main_program[hart].generate_instr_stream()` converts the instruction stream to string format. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] The broader program-generation flow includes header generation, GPR initialization, main and subprogram generation, host-interface instructions, and trap-handling support. RISC-V source class riscv_asm_program_gen, the brain behind ...
[6] `riscv_instr_gen_config` randomization decides the RISC-V extension, privilege mode, instruction counts, and whether instructions such as `ebreak`, `dret`, `fence`, and `wfi` are generated. RISC-V source class riscv_asm_program_gen, the brain behind ...
[7] If illegal-instruction or HINT-instruction ratios are zero, those instruction types are not generated. RISC-V source class riscv_asm_program_gen, the brain behind ...