Overview

BlackParrot is identified in the MICRO-54 paper Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation as one of three RISC-V cores evaluated, alongside CVA6 and BOOM. The paper's evaluation used Dromajo-based co-simulation and then re-ran the same binary set with Logic Fuzzer enabled to expose additional bugs. [Core evaluation target; Main results]

For BlackParrot, the simulated test set summarized in the paper included 215 RISC-V ISA tests and 150 random instruction-stream tests generated with riscv-dv. [BlackParrot test binaries]

Role in the Dromajo and Logic Fuzzer evaluation

The evaluation reports that Dromajo alone found nine bugs across the three evaluated RISC-V cores. Enabling Logic Fuzzer increased the exposed bug count to thirteen without adding new tests; the same tests listed in the paper's test-binary table were used. [Main results]

The BlackParrot-specific entries in the paper's bug summary are B7 through B12. The summary table marks all six BlackParrot entries as reported and fixed. Four of these BlackParrot bugs are shown as found by Dromajo alone, while two are shown as exposed with Dromajo plus Logic Fuzzer. [BlackParrot bug summary]

Reported BlackParrot issues

The paper describes several BlackParrot-specific issues:

• B7: integer divide sign-extension handling. BlackParrot's integer divide unit mishandled signed 32-bit division and remainder operations such as divw and remw. The paper states that the lower 32-bit source operands should be treated as signed values, but the implementation treated operands as unsigned. [B7 integer divide]
• B8: illegal instruction not trapped. The BlackParrot decoder did not trap an invalid instruction whose binary encoding resembled jalr but had a nonzero func3 sub-opcode. The paper notes that the RISC-V ISA defines jalr with sub-opcode zero and that invalid sub-opcodes should trigger an illegal-instruction exception. [B8 illegal instruction]
• B9: jalr least-significant-bit handling. BlackParrot did not clear the least-significant bit of a calculated jalr target address, even though the paper states that the RISC-V ISA requires that bit to be cleared. Dromajo flagged the resulting program-counter mismatch after jalr execution. [B9 JALR target]
• B10: speculative long-latency instruction commit. A Dromajo mismatch on a load was traced to long-latency instructions marked for flushing that later completed and wrote back because of an invalid poison bit. The paper says the issue could manifest when the pipeline flushed on exceptions. [B10 poison bit]
• Logic Fuzzer-exposed backend/frontend FIFO issue. The paper describes a BlackParrot FIFO between the backend and frontend used for commands such as PC redirect and state reset. When Logic Fuzzer inserted artificial backpressure by pulling the FIFO ready signal low, Dromajo observed BlackParrot committing instructions with the wrong PC. The designer attributed the issue to the backend being unable to handle backpressure because there were no stalling points past decode, allowing backend commands to be lost if the queue was not ready. [FIFO backpressure issue]
• Logic Fuzzer-exposed irregular memory-region hang. The paper also describes a bug exposed by generating irregular addresses from BlackParrot's Branch Target Buffer. A generated address mapped to off-chip memory and caused a complete system freeze. According to the paper, BlackParrot decoded the address and routed it to a tile device such as cfg or clint; if no device matched, the system hung. [BTB irregular address issue]

Related repository context

A public GitHub repository, black-parrot-hdk/zynq-parrot, is described as "BlackParrot on Zynq." Its public metadata lists Tcl as the repository language, 55 stars, 30 forks, and an update timestamp of 2026-04-21. [Zynq Parrot repository]