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riscv-tests

Tool WIKI v1 · 5/30/2026

riscv-tests is the C-language GitHub repository `riscv-software-src/riscv-tests`, used as a RISC-V test-binary suite in published comparisons of RISC-V testing frameworks. In the TestRIG paper, riscv-tests is evaluated by running its binaries through the Sail RISC-V model for RV32IMC and RV64IMAFDCZicsr coverage, and it is compared with QCVEngine/TestRIG and RISCV-DV.

Overview

riscv-tests is a C-language GitHub repository under riscv-software-src/riscv-tests. The public repository metadata reports 1,197 stars, 545 forks, and a last update timestamp of 2026-05-27T08:41:44Z.[1]

Role in RISC-V testing comparisons

The TestRIG paper, Randomized Testing of RISC-V CPUs using Direct Instruction Injection, uses riscv-tests as one of the comparison baselines alongside QCVEngine/TestRIG and RISCV-DV.[2] In that evaluation, the authors measure coverage for two RISC-V architecture configurations: RV32IMC and RV64IMAFDCZicsr.[2]

For riscv-tests, the paper measures coverage by running the test binaries on the Sail RISC-V model. For RV32IMC, the measured coverage includes the Sail model coverage of the I, M, and C extension instructions and general-purpose registers. For RV64IMAFDCZicsr, the measured coverage includes I, M, A, F, D, C, and CSR instructions, plus general-purpose and floating-point registers.[2]

Reported comparison points

The TestRIG paper reports that RV32IMC results were similar across QCVEngine, riscv-tests, and RISCV-DV, which the authors interpret as showing that QCVEngine can be a suitable alternative to unit testing and torture testing with respect to breadth of coverage.[2] For RV64IMAFDCZicsr, the paper reports more variance among the three frameworks.[2]

The same paper also compares counterexample-size complexity. It reports a median of 561 instructions for riscv-tests traces, compared with a median of 3 instructions for QCVEngine shrunken counterexamples and 15,339 for RISCV-DV sequences. The authors note that riscv-tests and RISCV-DV traces in this comparison do not allow shrinking.[3]

Related tools and publications

  • TestRIG / QCVEngine: compared with riscv-tests in coverage and counterexample-complexity evaluations.[2][3]
  • RISCV-DV: compared with riscv-tests and QCVEngine/TestRIG in the same paper.[2][3]
  • Randomized Testing of RISC-V CPUs using Direct Instruction Injection: the publication providing the cited comparison evidence.[2][3]

LINKED ENTITIES

3 links
TestRIG COMPARES_WITH
Randomized Testing of RISC-V CPUs using Direct Instruction Injection COMPARES_WITH
riscv-dv COMPARES_WITH

CITATIONS

3 sources
3 citations
[1] riscv-tests is the GitHub repository riscv-software-src/riscv-tests, implemented primarily in C, with 1,197 stars, 545 forks, and an update timestamp of 2026-05-27T08:41:44Z in the provided public metadata. riscv-software-src/riscv-tests
[2] The TestRIG paper evaluates riscv-tests alongside QCVEngine/TestRIG and RISCV-DV for RV32IMC and RV64IMAFDCZicsr coverage, measuring riscv-tests coverage by running its test binaries on the Sail RISC-V model. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[3] In the TestRIG paper's counterexample-size comparison, riscv-tests has a reported median trace length of 561 instructions, while QCVEngine has a median of 3 instructions and RISCV-DV has a median sequence length of 15,339; the paper notes that riscv-tests and RISCV-DV traces do not allow shrinking. Randomized Testing of RISC-V CPUs using Direct Instruction Injection