Overview

riscv-tests is an Assembly-language GitHub repository under riscv-software-src/riscv-tests. The public repository metadata reports 1,219 stars, 553 forks, and a last update timestamp of 2026-07-10T10:13:49Z.[1]

Use as a regression baseline

Swimmer-RISCV

Swimmer-RISCV, a configurable C++ RISC-V instruction set simulator, uses the riscv-tests repository to run its regression test suite.[2] Its README recommends installing riscv-tools and setting the $RISCV environment variable so that riscv-tests can be located, then driving Swimmer-RISCV against the generated test binaries.[2] At the time of that README snapshot, Swimmer-RISCV reports 10 of 402 patterns in riscv-tests failing, listing the following failing patterns:[2]

Multi-core UVM verification (Barcelona Zettascale Lab)

In the RISC-V Summit Europe 2025 abstract Verification of a RISC-V system with multiple cores, the authors describe a UVM-based verification flow for a multi-core RISC-V design whose reference model is a modified Spike integrated through SystemVerilog DPI calls.[3] Their test corpus is described as a collection of regression tests composed of riscv-isa-tests, riscv-arch-tests (formerly compliance), internal RVV ISA tests, and UVM directed tests for JTAG and DMA interfaces.[3]

According to that abstract, the initial set of regression jobs used riscv-tests along with a few other directed tests.[3] The authors report that these were necessary but not sufficient to detect buggy updates in the code, which would cause a high number of failing tests in subsequent runs. As a solution they created a batch of random tests to complement the regression, later improved by selecting a handful of random tests that had uncovered difficult bugs, an approach they describe as "much robust."[3] The bulk of the tests in the final flow come from the random binary generator riscv-dv, which they modified to provide full support of RVV 1.0.0 and to add options for finer control over the kinds of instructions generated.[3] The abstract explicitly credits tools including Spike, riscv-dv, and riscv-tests as beneficial to the community and a foundation for their flow.[3]

Role in RISC-V testing comparisons

The TestRIG paper, Randomized Testing of RISC-V CPUs using Direct Instruction Injection, uses riscv-tests as one of the comparison baselines alongside QCVEngine/TestRIG and RISCV-DV.[4] In that evaluation, the authors measure coverage for two RISC-V architecture configurations: RV32IMC and RV64IMAFDCZicsr.[4]

For riscv-tests, the paper measures coverage by running the test binaries on the Sail RISC-V model. For RV32IMC, the measured coverage includes the Sail model coverage of the I, M, and C extension instructions and general-purpose registers. For RV64IMAFDCZicsr, the measured coverage includes I, M, A, F, D, C, and CSR instructions, plus general-purpose and floating-point registers.[4]

Reported comparison points

The TestRIG paper reports that RV32IMC results were similar across QCVEngine, riscv-tests, and RISCV-DV, which the authors interpret as showing that QCVEngine can be a suitable alternative to unit testing and torture testing with respect to breadth of coverage.[4] For RV64IMAFDCZicsr, the paper reports more variance among the three frameworks.[4]

The same paper also compares counterexample-size complexity. It reports a median of 561 instructions for riscv-tests traces, compared with a median of 3 instructions for QCVEngine shrunken counterexamples and 15,339 for RISCV-DV sequences. The authors note that riscv-tests and RISCV-DV traces in this comparison do not allow shrinking.[5]

Related tools and publications

• Swimmer-RISCV: configurable C++ RISC-V instruction set simulator that drives its regression suite using riscv-tests.[2]
• TestRIG / QCVEngine: compared with riscv-tests in coverage and counterexample-complexity evaluations.[4][5]
• RISCV-DV: compared with riscv-tests and QCVEngine/TestRIG in the TestRIG paper; also used together with riscv-tests as the random-test complement in the multi-core UVM verification flow.[3][4][5]
• Spike (riscv-isa-sim): RISC-V ISA simulator used as the reference model in the multi-core UVM flow alongside riscv-tests.[3]
• Randomized Testing of RISC-V CPUs using Direct Instruction Injection: the publication providing the TestRIG comparison evidence.[4][5]
• Verification of a RISC-V system with multiple cores: RISC-V Summit Europe 2025 abstract describing the use of riscv-tests as an initial regression set within a broader UVM/Spike/riscv-dv flow.[3]