Overview

RISC-V RTG is identified in the cited TestRIG paper as an example of a RISC-V test generator. The mention appears in the context of model-based random testing, where generated instruction sequences are used to find divergences between a reference model and a processor implementation.

Verification context

The cited paper distinguishes model-based random testing from formal equivalence proof. It states that these testing approaches cannot prove equivalence between a formal model and an implementation, but can refute equivalence by finding counterexamples. Within that context, directed-random test-sequence generation is described as useful for debugging pipeline and memory bugs and for uncovering unexpected divergences in implementation behavior.

Position among RISC-V test generators

The paper notes that multiple RISC-V test generators exist and gives RISC-V RTG as an example. It then contrasts this with RISCV-DV, which the paper describes as the most advanced RISC-V sequence generator in that category. The evidence does not provide further details about RISC-V RTG's implementation, supported ISA subsets, or generation strategy.