RISC-V RTG

Tool

RISC-V RTG is referenced as a RISC-V test generator in a discussion of model-based random testing for processor verification. The available evidence identifies it as one of multiple RISC-V test generators and contrasts the broader tool category with formal verification approaches.

First seen 5/29/2026

Last seen 6/3/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

RISC-V RTG is identified in the cited TestRIG paper as an example of a RISC-V test generator. The mention appears in the context of model-based random testing, where generated instruction sequences are used to find divergences between a reference model and a processor implementation.

Verification context

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections

Randomized Instruction Generation implements → 90% 1e

RISC-V RTG is a random test generator for RISC-V processors.

TestRIG compares with → 70% 1e

RISC-V RTG is mentioned as one of multiple test generators for RISC-V, serving as a comparison point.

LINKED ENTITIES

1 links

riscv-dv same_domain_as The evidence names both RISC-V RTG and RISCV-DV as RISC-V test/sequence generators in the same model-based random testing discussion.

CITATIONS

4 sources

4 citations — click to collapse

[1] RISC-V RTG is identified as an example of a RISC-V test generator. Randomized Testing of RISC-V CPUs using Direct

[2] Model-based random testing can refute equivalence by finding counterexamples, but does not prove equivalence between a formal model and an implementation. Randomized Testing of RISC-V CPUs using Direct

[3] Directed-random test-sequence generation has been used to debug pipeline and memory bugs and to uncover unexpected divergences in implementation behavior. Randomized Testing of RISC-V CPUs using Direct

[4] The cited paper describes RISCV-DV as the most advanced RISC-V sequence generator in the discussed category. Randomized Testing of RISC-V CPUs using Direct