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Embench

Tool WIKI v1 · 5/29/2026

Embench is a C-based benchmark tool/repository used for performance evaluation in processor and simulator work. In the provided OpenVADL/QEMU generation evidence, Embench workloads are used to compare generated QEMU frontends against QEMU baselines for RISC-V 64 IM and AArch64.

Overview

Embench is represented by the main GitHub repository embench/embench-iot, whose primary language is C. The repository is the main Embench repository and, in the provided public metadata, has 320 stars and 137 forks as of its latest listed update on 2026-05-28.

Use in simulator evaluation

Embench appears in the evaluation of Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL. The slide deck reports Embench-based relative runtime measurements for generated QEMU frontends, with lower values being better and QEMU used as the baseline.

Two evaluated target settings are shown:

  • RISC-V 64 (IM) Embench - QEMU Relative
  • AArch64 Embench - QEMU Relative

The same evidence states that OpenVADL can automatically generate QEMU frontends from VADL specifications by lowering the VIAM intermediate representation to QEMU TCG operations, and that the generated frontend achieved up to 44% lower runtime than upstream in the reported evaluation context.

Workloads shown in the evidence

The RISC-V 64 (IM) Embench chart includes workloads such as aha-mont64, crc32, cubic, edn, huffbench, matmult-int, md5sum, minver, nbody, nettle-aes, nettle-sha256, nsichneu, picojpeg, primecount, qrduino, sglib-combined, slre, st, statemate, tarfind, ud, and wikisort.

The AArch64 Embench chart includes workloads such as aha-mont64, crc32, edn, huffbench, matmult-int, md5sum, nettle-aes, nettle-sha256, nsichneu, picojpeg, primecount, qrduino, sglib-combined, slre, and tarfind.

Repository

CITATIONS

4 sources
4 citations
[1] The main Embench repository is `embench/embench-iot`, uses C, and has the listed GitHub metadata of 320 stars, 137 forks, and latest update timestamp 2026-05-28T15:39:05Z. embench/embench-iot
[2] The OpenVADL QEMU-generation slide deck reports Embench-based QEMU-relative runtime evaluations for RISC-V 64 (IM) and AArch64. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] The slide deck states that generated OpenVADL QEMU frontends are produced by lowering VIAM to TCG operations and reports up to 44% lower runtime than upstream in the evaluation context. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] The evidence lists the named Embench workloads used in the RISC-V 64 (IM) and AArch64 evaluation charts. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL