Overview

In the cross-level processor verification flow described in Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging, the Comparator is responsible for finding functional differences between an RTL processor core and a reference Instruction Set Simulator (ISS).

Role in the verification flow

The Comparator operates after the RTL core and the ISS execute instructions in the co-simulation setup. The paper describes a flow in which the RTL core and ISS write execution results to separated memories, while other components such as the Coverage-Observer and Instruction-Injector guide randomized instruction generation. Within this flow, the Comparator checks whether the RTL-Core and ISS behave consistently.

Comparison method

The Comparator compares register values produced by the ISS and the RTL-Core. Because the two models may not have identical timing behavior, direct cycle-by-cycle matching is not sufficient. To address this, the Comparator logs value changes and continuously compares the two changes at the same position. This positional comparison is used to align observations even when the RTL core and ISS execute with different timing.

Failure handling

If the Comparator detects any difference between the compared register-value changes, it terminates the simulation. In this role, it acts as the checker that turns a functional mismatch between the implementation model and the reference ISS into a verification failure.

Relationship to ISS

The Comparator depends on the ISS as the reference source of architectural state. In the described setup, the ISS provides the execution state against which the RTL core's register changes are compared.